IP-10GETHERNET Altera, IP-10GETHERNET Datasheet - Page 5

• Manufacturer Part Number: IP-10GETHERNET
• Description: IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
• Manufacturer: Altera

Specifications of IP-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Revision History
Table 1–2. 10-Gbps Ethernet Performance and Resource Utilization—Stratix IV Device
Table 1–3. 10-Gbps Ethernet Performance and Resource Utilization—Arria II GX Device
1.3. Revision History
Table 1–4. New Features and Device Support History (Part 1 of 2)
© July 2010 Altera Corporation
Soft XAUI only
10.0 July 2010
9.1 December 2009
XAUI
Yes
Soft XAUI
Soft XAUI
XAUI
Yes
Yes
Release
(eight-b
words)
FIFO
256
yte
(eight-b
words)
FIFO
256
256
256
256
yte
—
MDIO
Yes
Table 1–2
targeting a Stratix IV (EP4SGX70DF29C3) device.
Table 1–3
targeting a Arria
Table 1–4
■
■
■
■
■
Added support for pause frame control (PFC). Frames can
be passed to the user interface (no internal support for the
pause control).
Added support for optional error correcting code (ECC) in
memories in the Soft XAUI PC and the transmit (Tx) and
receive (Rx) FIFOs on Stratix IV GX devices.
For the hard PCS, the local fault register is now asserted
after reset until the link is up.
On the XGMII interface, the Tx now transmits with a clock
shifted 90
shifted by 90
Corrected address for linkFaultDetect register.
MDIO
Yes
Yes
Yes
Yes
—
Statistics
Counter
Yes
shows the typical expected performance, using the Quartus II software v9.1
shows the typical expected performance, using the Quartus II software v9.1
summarizes the new feature and device support history for this IP core.
Statistics
°
Counter
and the Rx interface expects a clock that is
Yes
Yes
Yes
Yes
°
—
.
®
ECC
No
II GX (EP2AGX45CU17C5) device.
New Features
ECC
Yes
Yes
No
No
No
Combinational
Combinational
ALUTs
5,670
10,080
ALUTs
5,666
6,808
2,545
8,136
Registers
5,346
Logic
Registers
Logic
5,346
6,119
2,198
7,478
8,409
Avalon-
MM
269
Avalon
-MM
HardCopy
HardCopy IV
230
187
177
180
—
Device Support
f
Added
MAX
Avalon-
f
—
MAX
209
Avalon
ST
(MHz)
®
220
175
252
175
-ST
—
(MHz)
10-Gbps Ethernet IP Datasheet
III
System
System
Clock
156.25
Clock
199
Preliminary
Preliminary
197
175
188
168
Device Support
Level
—
Memory
Memory
M9K
M9K
10
13
4
4
6
6
(1)
1–3