IP-10GETHERNET Altera, IP-10GETHERNET Datasheet - Page 64

• Manufacturer Part Number: IP-10GETHERNET
• Description: IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
• Manufacturer: Altera

Specifications of IP-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

3–38
Table 3–16. Control Interface Register Map (Part 7 of 7)
3.6.1. Command_Config Register
Table 3–17. Command_Config Register Bit Descriptions (Part 1 of 3)
10-Gbps Ethernet IP Functional Description
0x344
0x348
Address
Bit(s)
Offset
0
1
2
3
6
4
5
TX_ENA
RX_ENA
XON_GEN
Reserved
PROMIS_EN
PAD_EN
CRC_FWD
ALTGX status1
Shadow MDIO
Bit Name
Table 3–17
register.
Name
Access
describes the function of each bit and field in the command_config
RW
RW
RW
RW
RW
RW
—
■
■
■
Transmit enable. Setting this bit to 1 enables the transmit datapath. This bit is
cleared following a hardware or software reset. Refer to the SW_RESET bit
description.
Receive enable. Setting this bit to 1 enables the receive datapath. This bit is
cleared following a hardware or software reset. See the the SW_RESET bit
description.
Pause frames generation. When this bit is set to 1, the IP core generates a
pause frame with a pause quanta of 0, independent of the receive FIFO status.
Reserved.
Promiscuous enable. Setting this bit to 1 enables promiscuous operation in
which the destination address of the receive frame is not checked.
Pad enable. Setting this bit to 1 enables pad removal in receive frames. The
IP core removes receive frame padding before forwarding the frames to the
user application. Transmit frames are always padded and this bit has no
effect.
Receive CRC forwarding.
Status of the transceivers (XAUI
only).
■
■
■
■
For more information, refer to the
“Stratix IV Transceiver
chapter in the Stratix IV Device
Handbook.
Stores the last read value from the
MDIO access.
If this bit is set to 1, the IP core forwards the CRC field to the user
application.
If this bit is set to 0, the IP core removes the CRC field from the frame
before forwarding the frame to the user application.
This bit is ignored if the PAD_EN bit is 1. In this case, the IP core checks
the CRC field and removes it from the frame before forwarding the frame
to the user application.
7:0 rx_disperr
15:8 rx_errdetect
23:16 rx_patterndetect
31:24 rx_syncstatus
Description
Architecture”
Description
Access
RO
—
© July 2010 Altera Corporation
HW Reset
—
—
Register Descriptions
SW Reset
—
—