IP-10GETHERNET Altera, IP-10GETHERNET Datasheet - Page 12

• Manufacturer Part Number: IP-10GETHERNET
• Description: IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
• Manufacturer: Altera

Specifications of IP-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

2–6
Table 2–1. Variation Options (Part 2 of 2)
2.2.2. FIFO Options
Table 2–2. FIFO Options
Getting Started with the 10-Gbps Ethernet IP
Soft XAUI only
MAC only
Receiver FIFO size
Transmitter FIFO size
Mode
Soft XAUI Tx PLL Type
Parameter
Parameter Settings
In most applications, the client side interface of the IP core includes a FIFO between
the client and the MAC.
include the FIFO in the IP core.
8,16,32,64,128,256,5
12,1024,4096,8192
Store forward
Fill level
Value
The Soft XAUI only option is only available on Stratix IV devices. It combines a
10GBASE-X XAUI soft PCS and a hard PMA. This configuration allows the design
to use all the available transceivers. The soft XAUI PCS includes the transceiver
megafunction and the reset sequence controller, which applies the transceiver
reset signals with the required constraints.
These options are only available when you select MAC + Soft XAUI or Soft XAUI
Only. These are two different PLLs:
CMU–(clock multiplier unit) designed to achieve low Tx channel-to-channel skew.
ATX–(auxiliary transmit) designed to improve jitter performance.
For more information refer to
PLLS in Stratix IV GX and GT Devices
Handbook.
Creates a IP core that includes the MAC with an Avalon-ST interface on the client
side and 64-bit XGMII interface running at 156.25MHz on network side. This
interface functions like an SDR interface.
Selects the depth of the FIFO in 8-byte words in each direction. The
usable FIFO size is <size> – 1.
The packet information passes from the write side to the read side only
when the end of packet (EOP) is asserted on the write side. When you
select Store forward, you should select the FIFO size to accommodate the
longest possible frame in the system with some overhead. Altera
recommends twice the maximum possible frame size as a minimum.
In most cases, Store forward mode increases the latency and requires a
deeper FIFO.
In Fill level mode, the FIFO begins passing data to the read side when a
configurable number of bytes are available or an EOP is received.
Table 2–2
describes the options that are available when you
AN 578: Manual Placement of CMU PLLs and ATX
Chapter 2: Getting Started with the 10-Gbps Ethernet IP
Description
and
Description
Volume 3
of the Stratix IV Device
© July 2010 Altera Corporation
IP Core Parameterization