IP-10GETHERNET Altera, IP-10GETHERNET Datasheet - Page 59

• Manufacturer Part Number: IP-10GETHERNET
• Description: IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
• Manufacturer: Altera

Specifications of IP-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Register Descriptions
Table 3–16. Control Interface Register Map (Part 2 of 7)
© July 2010 Altera Corporation
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
Address
Offset
frm_length
pause_quant
rx_almost_empty_off
rx_almost_empty_on
tx_almost_empty_off
tx_almost_empty_on
rx_almost_full_off
rx_almost_full_on
tx_almost_full_off
tx_almost_full_on
Name
14-bit maximum frame length. The
receive logic uses this value to check
frames. Typical value is 1518.
Bits 14 –31 are reserved.
16-bit pause quanta. The pause
quanta is used in each pause frame
sent to a remote Ethernet device, in
increments of 512 Ethernet bit times.
Bits 16 –31 are reserved.
FIFO almost empty off threshold. Bits
12 –31 are unused.
FIFO almost empty on threshold. The
number writeable bits depends on the
FIFO size. For example, if the FIFO has
1024 bytes, 10 bits are writeable. The
bottom 3 bits are ignored so that a
threshold of 0x100 and 0x102 is the
same.
FIFO almost empty off threshold. The
number writeable bits depends on the
FIFO size. The bottom 3 bits are
ignored so that a threshold of 0x100
and 0x102 is the same.
FIFO almost empty on threshold. The
number writeable bits depends on the
FIFO size. The bottom 3 bits are
ignored so that a threshold of 0x100
and 0x102 is the same.
FIFO almost-full threshold. The
number writeable bits depends on the
FIFO size. The bottom 3 bits are
ignored so that a threshold of 0x100
and 0x102 is the same.
FIFO almost-full threshold. The
number writeable bits depends on the
FIFO size. The bottom 3 bits are
ignored so that a threshold of 0x100
and 0x102 is the same.
Transmit FIFO almost-full threshold.
The number writeable bits depends
on the FIFO size. The bottom 3 bits
are ignored so that a threshold of
0x100 and 0x102 is the same.
Transmit FIFO almost-full threshold.
The number writeable bits depends
on the FIFO size. The bottom 3 bits
are ignored so that a threshold of
0x100 and 0x102 is the same.
Description
Access
10-Gbps Ethernet IP Functional Description
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
HW Reset
1518
0
0
0
0
0
0
0
0
0
SW Reset
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