IP-10GETHERNET Altera, IP-10GETHERNET Datasheet - Page 61

• Manufacturer Part Number: IP-10GETHERNET
• Description: IP CORE - 10 Gbps Ethernet MAC PCS PMA Reference Design
• Manufacturer: Altera

Specifications of IP-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Register Descriptions
Table 3–16. Control Interface Register Map (Part 4 of 7)
© July 2010 Altera Corporation
0x0AC
0x0B0
0x0B4
0x0B8
0x0BC
0x0C0
0x0C4
0x0C8
0x0CC
0x0D0
0x0D4
0x0D8
0x0DC
0x0E0
0x0E4
0x0E8
Address
Offset
etherStatsDropEvents
etherStatsOctets_0
etherStatsPkts_0
etherStatsUndersize
Pkts
etherStatsOversizePkts See
etherStatsPkts64Octets See
etherStatsPkts65to127
Octets
etherStatsPkts128to255
Octets
etherStatsPkts256to511
Octets
etherStatsPkts512to102
3Octets
etherStatsPkts1024to15
18Octets
etherStatsPkts1519toX
Octets
etherStatsJabbers
etherStatsFragments
Reserved
linkFaultDetect
Name
See
See
See
See
See
See
See
See
See
See
See
See
Unused.
Link remote and local fault detection
according to IEEE 802.3ae:
■
■
■
All other bits are currently unused.
Bit[0] =1'b1 and indicates a local
fault has been detected
Bit[1] = 1'b1 and indicates a
remote fault has been detected
Bit [1:0] = 2'b00 and indicates link
is OK
Table 3–19 on page
Table 3–19 on page
Table 3–20 on page
Table 3–20 on page
Table 3–20 on page
Table 3–20 on page
Table 3–20 on page
Table 3–20 on page
Table 3–20 on page
Table 3–20 on page
Table 3–20 on page
Table 3–20 on page
Table 3–20 on page
Table 3–20 on page
Description
3–41.
3–41.
3–42.
3–42.
3–42.
3–42.
3–42.
3–42.
3–42.
3–42.
3–42.
3–42.
3–42.
3–42.
Access
10-Gbps Ethernet IP Functional Description
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
HW Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SW Reset
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3–35