ADUC7034BCPZ-RL Analog Devices Inc, ADUC7034BCPZ-RL Datasheet - Page 10

• Manufacturer Part Number: ADUC7034BCPZ-RL
• Description: IC,Battery Management,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7034BCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7034
TIMING SPECIFICATIONS
SPI Timing Specifications
Table 2. SPI Master Mode Timing—Phase Mode = 1
Parameter
t
t
t
t
t
t
t
t
t
1
2
SL
SH
DAV
DSU
DHD
DF
DR
SR
SF
t
t
HCLK
UCLK
depends on the clock divider (CD) bits in the POWCON MMR. t
= 48.8 ns and corresponds to the 20.48 MHz internal clock from the PLL before the clock divider.
Description
SCLK low pulse width
SCLK high pulse width
Data output valid after SCLK edge
Data input setup time before SCLK edge
Data input hold time after SCLK edge
Data output fall time
Data output rise time
SCLK rise time
SCLK fall time
(POLARITY = 0)
(POLARITY = 1)
SCLK
SCLK
MOSI
MISO
1
1
t
DAV
t
Figure 2. SPI Master Mode Timing—PHASE Mode = 1
SH
2
t
DSU
2
MSB IN
HCLK
MSB
t
DHD
= t
Min
0
3 × t
Rev. B | Page 10 of 136
t
SL
UCLK
UCLK
/2
t
DF
CD
.
t
DR
BITS [6:1]
BITS [6:1]
Typ
(SPIDIV + 1) × t
(SPIDIV + 1) × t
3.5
3.5
3.5
3.5
t
SR
HCLK
HCLK
t
LSB IN
SF
LSB
Max
(2 × t
UCLK
) + (2 × t
HCLK
)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns