ADUC7034BCPZ-RL Analog Devices Inc, ADUC7034BCPZ-RL Datasheet - Page 65

• Manufacturer Part Number: ADUC7034BCPZ-RL
• Description: IC,Battery Management,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7034BCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

POWCON Register
Name:
Address:
Default Value:
Access:
Function:
Table 45. POWCON MMR Bit Designations
Bit
7
6
5
4
3
2 to 0
POWCON
0xFFFF0408
0x079
Read/write
This 8-bit register allows user code to dynamically enter various low power modes and modify the clock divider that
controls the speed of the ARM7TDMI core.
Description
Precision 131 kHz input enable.
Set by the user to enable the precision 131 kHz input enable. The precision 131 kHz oscillator must also be enabled
using HVCFG0[6]. Setting this bit increases current consumption by approximately 50 μA and should be disabled when
not in use.
Cleared by the user to power down the precision 131 kHz input enable.
XTAL power-down.
Set by the user to enable the external crystal circuitry.
Cleared by the user to power down the external crystal circuitry.
PLL power-down. Timer peripherals power down if driven from the PLL output clock. Timers driven from an active clock
source remain in normal power mode.
Set by default, or set by hardware upon a wake-up event.
Cleared to 0 to power down the PLL. The PLL cannot be powered down if either the core or peripherals are enabled;
therefore, Bit 3, Bit 4, and Bit 5 must be cleared simultaneously.
Peripherals power-down. The peripherals that are powered down by this bit are as follows: SRAM, Flash/EE memory and
GPIO interfaces, and SPI and UART serial ports.
Set by default, or set by hardware upon a wake-up event. The wake-up timer (Timer2) can be active if the device is
driven from the low power oscillator even if this bit is set.
Cleared to power down the peripherals. The peripherals cannot be powered down if the core is enabled; therefore, Bit 3
and Bit 4 must be cleared simultaneously. LIN can respond to wake-up events even if this bit is cleared.
Core power-down. If user code powers down the MCU, include a dummy MCU cycle after the power-down command is
written to POWCON.
Set by default, or set by hardware on a wake-up event.
Cleared to power down the ARM core.
Core clock divider (CD) bits.
000 = 20.48 MHz, 48.83 ns.
001 = 10.24 MHz, 97.66 ns. (This is the default setting at power up.)
010 = 5.12 MHz, 195.31 ns.
011 = 2.56 MHz, 390.63 ns.
100 = 1.28 MHz, 781.25 ns.
101 = 640 kHz, 1.56 μs.
110 = 320 kHz, 3.125 μs.
111 = 160 kHz, 6.25 μs.
Rev. B | Page 65 of 136
ADuC7034