ADUC7034BCPZ-RL Analog Devices Inc, ADUC7034BCPZ-RL Datasheet - Page 49

• Manufacturer Part Number: ADUC7034BCPZ-RL
• Description: IC,Battery Management,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7034BCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADC Filter Register
Name:
Address:
Default Value:
Access:
Function:
Note:
Table 38. ADCFLT MMR Bit Designations
1
2
Bit
15
14
13 to 8
7
6 to 0
Due to limitations on the digital filter internal data path, there are some limitations on the combinations of the sinc3 decimation factor (SF) and the averaging factor (AF)
that can be used to generate a required ADC output rate. This restriction limits the minimum ADC update in normal power mode to 4 Hz or 1 Hz in lower power mode.
In low power mode or low power plus mode, the ADC is driven directly by the low power 131 kHz oscillator, not by 512 kHz. All f
(approximately).
ADCFLT
0xFFFF0518
0x0007
Read/write
The ADC filter MMR is a 16-bit register that controls the speed and resolution of the on-chip ADCs.
If ADCFLT is modified, the current and voltage/temperature ADCs are reset.
Description
Chop enable.
Set by the user to enable system chopping of all active ADCs. When this bit is set, the ADC has very low offset errors and
drift, but the ADC output rate is reduced by a factor of 3 if AF = 0 (see the sinc3 decimation factor, Bits[6:0], in this table). If
AF > 0, the ADC output update rate is the same with chop enabled or disabled. When chop is enabled, the settling time
is two output periods.
Cleared by user code to disable system chopping.
Running average.
Set by the user to enable a running-average-by-two function, which reduces ADC noise. This function is automatically
enabled when chopping is active and is an optional feature when chopping is inactive. The ADC output rate is not
reduced if the running average function is enabled when chopping is inactive; instead, the settling time is increased by
one conversion period.
Cleared by the user to disable the running average function.
Averaging factor (AF). The values written to these bits are used to implement a programmable first-order sinc3 postfilter.
The averaging factor can further reduce ADC noise at the expense of output rate, as described in the sinc3 decimation
factor, Bits[6:0], in this table.
Sinc3 modify. Set by the user to modify the standard sinc3 frequency response and increase the stop-band rejection of
the filter by approximately 5 dB. This is achieved by inserting a second notch (NOTCH2) at f
f
Sinc3 decimation factor (SF).
filter. The output rate from the sinc3 filter is given by f
and the averaging factor (AF) = 0. This is valid for all SF values ≤ 125.
For SF = 126, f
For SF = 127, f
For information on calculating the f
NOTCH
is the location of the first notch in the response.
ADC
ADC
is forced to 60 Hz.
is forced to 50 Hz.
1
The value written in these bits controls the oversampling (decimation factor) of the sinc3
ADC
for SF (other than 126 and 127) and AF values, refer to Table 39.
Rev. B | Page 49 of 136
ADC
= (512,000/([SF + 1] × 64)) Hz
2
when the chop enable bit (Bit 15) = 0
ADC
calculations should be divided by 4
NOTCH2
= 1.333 × f
ADuC7034
NOTCH
, where