ADUC7034BCPZ-RL Analog Devices Inc, ADUC7034BCPZ-RL Datasheet - Page 30

• Manufacturer Part Number: ADUC7034BCPZ-RL
• Description: IC,Battery Management,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7034BCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7034
CODE EXECUTION TIME FROM SRAM AND
FLASH/EE
This section describes SRAM and Flash/EE access times during
execution for applications where execution time is critical.
Execution from SRAM
Fetching instructions from SRAM takes one clock cycle because
the access time of the SRAM is 2 ns, and a clock cycle is 49 ns
minimum. However, when the instruction involves reading or
writing data to memory, one extra cycle must be added if the
data is in SRAM. If the data is in Flash/EE, two cycles must be
added: one cycle to execute the instruction and two cycles to
retrieve the 32-bit data from Flash/EE. A control flow instruction,
such as a branch instruction, takes one cycle to fetch and two
cycles to fill the pipeline with the new instructions.
Execution from Flash/EE
In Thumb mode, where instructions are 16 bits, one cycle is
needed to fetch any instruction.
In ARM mode with CD = 0, two cycles are needed to fetch the
32-bit instructions. With CD > 0, no extra cycles are required
for the fetch because the Flash/EE memory continues to be
clocked at full speed. In addition, some dead time is needed
before accessing data for any value of CD bits.
Timing is identical in both modes when executing instructions
that involve using the Flash/EE for data memory. If the instruction
to be executed is a control flow instruction, an extra cycle is
needed to decode the new address of the program counter, and
then four cycles are needed to fill the pipeline if CD = 0.
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A data processing instruction involving only the core register
does not require any extra clock cycles. Data transfer instructions
are more complex and are summarized in Table 17.
Table 17. Typical Execution Cycles in ARM/Thumb Mode
Instructions
LD
LDH
LDM/PUSH
STR
STRH
STRM/POP
With 1 < N ≤ 16, N is the number of data to load or store in the
multiple load/store instruction.
By default, Flash/EE code execution is suspended during any
Flash/EE erase or write cycle. A page (512 bytes) erase cycle
takes 20 ms and a write (16 bits) word command takes 50 μs.
However, the Flash/EE controller allows erase/write cycles to
be aborted if the ARM core receives an enabled interrupt during
the current Flash/EE erase/write cycle. The ARM7 can, therefore,
immediately service the interrupt and then return to repeat the
Flash/EE command. The abort operation typically requires 10 clock
cycles. If the abort operation is not feasible, the user can run
Flash/EE programming code and the relevant interrupt routines
from SRAM to allow the core to immediately service the interrupt.
Fetch
Cycles
2/1
2/1
2/1
2/1
2/1
2/1
Dead
Time
1
1
N
1
1
N
Data Access
2
1
2 × N
2 × 50 μs
50 μs
2 × N × 50 μs