ADUC7034BCPZ-RL Analog Devices Inc, ADUC7034BCPZ-RL Datasheet - Page 81

• Manufacturer Part Number: ADUC7034BCPZ-RL
• Description: IC,Battery Management,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7034BCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Timer3 Control Register
Name:
Address:
Default Value:
Access:
Function:
Table 55. T3CON MMR Bit Designations
Bit
15 to 9
8
7
6
5
4
3 to 2
1
0
Set by user code to stop Timer3 when the peripherals are powered down using Bit 4 in the POWCON MMR.
Cleared by user code to enable Timer3 when the peripherals are powered down using Bit 4 in the POWCON MMR.
Description
Reserved. These bits are reserved and should be written as 0 by user code.
Count up/count down enable.
Set by user code to configure Timer3 to count up.
Cleared by user code to configure Timer3 to count down.
Timer3 enable.
Set by user code to enable Timer3.
Cleared by user code to disable Timer3.
Timer3 operating mode.
Set by user code to configure Timer3 to operate in periodic mode.
Cleared by user to configure Timer3 to operate in free running mode.
Watchdog timer mode enable.
Set by user code to enable watchdog mode.
Cleared by user code to disable watchdog mode.
Reserved. This bit is reserved and should be written as 0 by user code.
Timer3 clock (32.768 kHz) prescaler.
00 = source clock/1 (default).
01 = source clock/16.
10 = source clock/256.
11 = reserved.
Watchdog timer IRQ enable.
Set by user code to produce an IRQ instead of a reset when the watchdog reaches 0.
Cleared by user code to disable the IRQ option.
PD_OFF.
T3CON
0xFFFF0368
0x0000
Read/write
This 16-bit MMR configures the mode of operation of Timer3 as described in Table 55.
Rev. B | Page 81 of 136
ADuC7034