ADUC7034BCPZ-RL Analog Devices Inc, ADUC7034BCPZ-RL Datasheet - Page 58

• Manufacturer Part Number: ADUC7034BCPZ-RL
• Description: IC,Battery Management,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7034BCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7034
In ADC low power mode, the Σ-Δ modulator clock of the ADC
is no longer driven at 512 kHz, but is driven directly from the
on-chip low power 131 kHz oscillator. Subsequently, if normal
mode is used for the same ADCFLT configuration, all filter values
should be scaled by a factor of approximately 4. Therefore, it is
possible to configure the ADC for 1 Hz throughput in low power
mode. The filter frequency response for this configuration is
shown in Figure 27.
Table 42. Common ADCFLT Configurations
ADC Mode
Normal
Normal
Normal
Normal
Normal
Normal
Low Power
Low Power
Low Power
Figure 26. Typical Digital Filter Response at f
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
0
SF
0x1D
0x1F
0x07
0x07
0x03
0x00
0x10
0x10
0x1F
20
FREQUENCY (kHz)
AF
0x3F
0x16
0x00
0x00
0x00
0x00
0x03
0x09
0x3D
ADC
= 4 Hz (ADCFLT = 0xBF1D)
40
Other Config
Chop enabled
Chop enabled
None
Sinc3 modify
Running average
Running average
Chop enabled
Chop enabled
Chop enabled
6
0
Rev. B | Page 58 of 136
In general, it is possible to program different values of SF and
AF in the ADCFLT register and achieve the same ADC update
rate. However, in practical terms, users should consider the
trade-off between frequency response and ADC noise for any
value of ADCFLT. For optimum filter response and ADC noise
when using combinations of SF and AF, best practice suggests
choosing an SF in the range of 16 decimal to 40 decimal, or
0x10 to 0x28, and then increasing the AF value to achieve the
required ADC throughput. Table 42 provides information about
some common ADCFLT configurations.
Figure 27. Typical Digital Filter Response at f
ADCFLT
0xBF1D
0x961F
0x0007
0x0087
0x4003
0x4000
0x8310
0x8910
0xBD1F
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
0
2
4
6
FREQUENCY (kHz)
f
4 Hz
10 Hz
1 kHz
1 kHz
2 kHz
8 kHz
20 Hz
10 Hz
1 Hz
ADC
8
10
ADC
12
= 1 Hz (ADCFLT = 0xBD1F)
14
t
0.5 sec
0.2 sec
3 ms
3 ms
2 ms
0.5 ms
100 ms
200 ms
2 sec
SETTLE
16
18
2
0