ADUC7034BCPZ-RL Analog Devices Inc, ADUC7034BCPZ-RL Datasheet - Page 84

• Manufacturer Part Number: ADUC7034BCPZ-RL
• Description: IC,Battery Management,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7034BCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7034
GENERAL-PURPOSE I/O
The ADuC7034 features nine general-purpose bidirectional
input/output (GPIO) pins. In general, many of the GPIO pins have
multiple functions that can be configured by user code. By default,
the GPIO pins are configured in GPIO mode. All GPIO pins
have an internal pull-up resistor with a sink capability of 0.8 mA
and a source capability of 0.1 mA.
The nine GPIOs are grouped into three ports: Port0, Port1, and
Port2. Port0 is five bits wide. Port1 and Port2 are each two bits
wide. The GPIO assignment within each port is detailed in
Table 57. A typical GPIO structure is shown Figure 39.
External interrupts are present on GPIO_0, GPIO_5, GPIO_7,
and GPIO_8. These interrupts are level triggered and active
high. Because these interrupts are not latched, the interrupt
source must be present until either IRQSTA or FIQSTA are
interrogated. The interrupt source must be active for at least
one CD-divided core clock to guarantee recognition.
Rev. B | Page 84 of 136
All port pins are configured and controlled by four sets (one set
for each port) of four port-specific MMRs as follows:
•
•
•
•
where x corresponds to the port number (0, 1, or 2).
During normal operation, user code can control the function
and state of the external GPIO pins by these general-purpose
registers. All GPIO pins retain their external level (high or low)
during power-down (POWCON) mode.
GPxCON: Portx control register
GPxDAT: Portx configuration and data register
GPxSET: Data set Portx
GPxCLR: Data clear Portx
OUTPUT DRIVE ENABLE
1
ONLY AVAILABLE ON GPIO_0, GPIO_5, GPIO_7, AND GPIO_8.
GPxDAT[31:24]
GPxDAT[23:16]
OUTPUT DATA
GPxDAT[7:0]
INPUT DATA
GPIO IRQ
Figure 39. ADuC7034 GPIO
1
REG_DVDD
GPIO