ADUC7034BCPZ-RL Analog Devices Inc, ADUC7034BCPZ-RL Datasheet - Page 99

• Manufacturer Part Number: ADUC7034BCPZ-RL
• Description: IC,Battery Management,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7034BCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High Voltage Configuration1 Register
Name:
Address:
Default Value:
Access:
Function:
Table 74. HVCFG1 Bit Designations
Bit
7
6
5
4
3
2
1
0
HVCFG1
Indirectly addressed via the HVCON high voltage interface
0x00
Read/write
This 8-bit register controls the function of high voltage circuits on the ADuC7034. This register is not an MMR and does
not appear in the Complete MMR Listing section. It is accessed indirectly via the HVCON MMR, and data is indirectly
written to or read from this register via the HVDAT MMR.
Description
Voltage attenuator diagnostic enable bit.
Set to 1 to turn on a 1.29 μA current source, which adds 170 mV differential voltage to the voltage channel measurement.
Cleared to 0 to disable the voltage attenuator diagnostic.
High voltage temperature monitor. The high voltage temperature monitor is an uncalibrated temperature monitor
located on chip, close to the high voltage circuits. This monitor is completely separate from the on-chip precision
temperature sensor (controlled via ADC1CON[7:6]) and allows user code to monitor die temperature change close to
the hottest part of the ADuC7034 die. The monitor generates a typical output voltage of 600 mV at 25°C and has a
negative temperature coefficient of typically −2.1 mV/°C.
Set to 1 to enable the on-chip high voltage temperature monitor. When enabled, this voltage output temperature
monitor is routed directly to the voltage channel ADC.
Cleared to 0 to disable the on-chip high voltage temperature monitor.
Voltage channel short enable bit.
Set to 1 to enable an internal short (at the attenuator before the ADC input buffers) on the voltage channel ADC and
allows noise to be measured as a self-diagnostic test.
Cleared to 0 to disable an internal short on the voltage channel.
WU and STI readback enable bit.
Set to 1 to enable input capability on the external WU and STI pins. In this mode, a rising or falling edge transition on
the WU and STI pins generates a high voltage interrupt. When this bit is set, the state of the WU and STI pins can be
monitored via the HVMON register (HVMON[7] and HVMON[5]).
Cleared to 0 to disable input capability on the external WU/STI pins.
High voltage I/O driver enable bit.
Set to 1 to re-enable any high voltage I/O pins (LIN/BSD, STI, and WU) that have been disabled as a result of a short-
circuit current event lasting more than 20 μs for LIN/BSD and STI pins and more than 400 μs for the WU pin. This bit
must also be set to 1 to re-enable the WU and STI pins if they were disabled by a thermal event. It should be noted that
pending interrupts are not automatically cleared even if the event has passed; therefore, this bit must be manually set
to clear any pending interrupt generated by the short-circuit event and to re-enable the high voltage I/O pins.
Cleared to 0 automatically.
Enable/disable short-circuit protection (LIN/BSD and STI).
Set to 1 to enable passive short-circuit protection on the LIN pin. In this mode, a short-circuit event on the LIN/BSD pin
generates a high voltage interrupt, IRQ3 (if enabled in IRQEN[16]), and asserts the appropriate status bit in HVSTA but
does not disable the short-circuiting pin.
Cleared to 0 to enable active short-circuit protection on the LIN/BSD pin. In this mode during a short-circuit event, the
LIN/BSD pin generates a high voltage interrupt (IRQ3), asserts HVSTA[16], and automatically disables the short-
circuiting pin. When disabled, the I/O pin can only be re-enabled by writing to HVCFG1[3].
WU pin timeout (monoflop) counter enable/disable.
Set to disable the WU I/O timeout counter.
Cleared to enable a timeout counter that automatically deasserts the WU pin 1.3 sec after user code has asserted the
WU pin via HVCFG0[4].
WU open-circuit diagnostic enable.
Set to enable an internal WU I/O diagnostic pull-up resistor to the VDD pin, thus allowing detection of an open-circuit
condition on the WU pin.
Cleared to disable an internal WU I/O diagnostic pull-up resistor.
Rev. B | Page 99 of 136
ADuC7034