ADUC7034BCPZ-RL Analog Devices Inc, ADUC7034BCPZ-RL Datasheet - Page 80

• Manufacturer Part Number: ADUC7034BCPZ-RL
• Description: IC,Battery Management,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7034BCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7034
TIMER3—WATCHDOG TIMER
Timer3 has two modes of operation: normal mode and
watchdog mode. The watchdog timer is used to recover
from an illegal software state. When enabled, it requires
periodic servicing to prevent it from forcing a reset of the
processor.
Timer3 reloads the value from T3LD when Timer3 overflows.
Normal Mode
Timer3 in normal mode is identical to Timer0 in 16-bit mode
of operation, except for the clock source. The clock source is the
low power 32.768 kHz oscillator and is scalable by a factor of 1,
16, or 256.
Watchdog Mode
Watchdog mode is entered by setting T3CON[5]. Timer3
decrements from the timeout value present in the T3LD register
until 0 is reached. The maximum timeout is 512 sec, using a
maximum prescaler/256 and full scale in T3LD.
User software should not configure a timeout period of less
than 30 ms to avoid any conflict with Flash/EE memory page
erase cycles that require 20 ms to complete a single page erase
cycle and kernel execution.
If T3VAL reaches 0, a reset or an interrupt occurs, depending
on T3CON[1]. To avoid a reset or an interrupt event, any value
must be written to T3CLRI before T3VAL reaches 0. This
reloads the counter with T3LD and begins a new timeout period.
When watchdog mode is entered, T3LD and T3CON are
write protected. These two registers cannot be modified until
a power-on reset event resets the watchdog timer. After any
other reset event, the watchdog timer continues to count. The
watchdog timer should be configured by the initial lines of user
code to avoid an infinite loop of watchdog resets. User software
should only configure a minimum timeout period of 30 ms.
Timer3 is automatically halted during JTAG debug access and
only resumes counting after JTAG has relinquished control of
the ARM7 core. By default, Timer3 continues to count during
power-down. This can be disabled by setting Bit 0 in T3CON.
However, it is recommended to use the default value, that is,
the watchdog timer continues to count during power-down.
LOW POWER
32.768kHz
PRESCALER
1, 16, 256
Figure 37. Timer3 Block Diagram
Rev. B | Page 80 of 136
UP/DOWN COUNTER
16-BIT LOAD
TIMER3
VALUE
16-BIT
Timer3 Interface
The Timer3 interface consists of four MMRs:
•
•
•
Timer3 Load Register
Name: T3LD
Address: 0xFFFF0360
Default Value: 0x0040
Access: Read/write
Function: This 16-bit MMR holds the Timer3 reload value.
Timer3 Clear Register
Name: T3CLRI
Address: 0xFFFF036C
Access: Write only
Function: This 8-bit, write only MMR is written (with any
value) by user code to refresh (reload) Timer3 in watchdog
mode to prevent a watchdog timer reset event.
Timer3 Value Register
Name: T3VAL
Address: 0xFFFF0364
Default Value: 0x0040
Access: Read only
Function: This 16-bit, read only MMR holds the current Timer3
count value.
T3CON is a configuration MMR and is described in Table 55.
T3LD and T3VAL are 16-bit registers and hold 16-bit
unsigned integers. T3VAL is a read only register.
T3CLRI is an 8-bit register. Writing any value to this
register clears the Timer3 interrupt in normal mode or
resets a new timeout period in watchdog mode.
WATCHDOG RESET
TIMER3 IRQ