ADUC7034BCPZ-RL Analog Devices Inc, ADUC7034BCPZ-RL Datasheet - Page 120

• Manufacturer Part Number: ADUC7034BCPZ-RL
• Description: IC,Battery Management,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7034BCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7034
Bit
6
5
4
3
2
1
0
1
LIN Hardware Synchronization Control Register 1
Name:
Address:
Default Value:
Access:
Function:
Table 93. LHSCON1 MMR Bit Designations
Bit
7 to 4
3 to 0
In BSD mode, LHSCON0[6] is set to 1. Because of the finite propagation delay in the BSD transmit (from the MCU to the external pin) and receive (from the external pin
to the MCU) paths, user code must not switch between BSD write and read modes until the MCU confirms that the external BSD pin is deasserted. Failure to adhere to
this recommendation can result in the generation of an inadvertent break condition interrupt after user code switches from BSD write mode to BSD read mode. A stop
condition interrupt can be used to ensure that this scenario is avoided.
Description
Mode of operation bit.
Set to 1 by user code to select BSD mode of operation.
Cleared to 0 by user code to select LIN mode of operation.
Enable compare interrupt bit.
Set to 1 by user code to generate an LHS interrupt (IRQEN[7]) when the value in LHSVAL0 (the LIN synchronization bit timer) equals
the value in the LHSCMP register. The LHS compare interrupt bit (LHSSTA[3]) is set when this interrupt occurs. This configuration
is used in BSD write mode to allow user code to correctly time the output pulse widths of BSD bits to be transmitted.
Cleared to 0 by user code to disable compare interrupts.
Enable stop interrupt.
Set to 1 by user code to generate an interrupt when a stop condition occurs.
Cleared to 0 by user code to disable interrupts when a stop condition occurs.
Enable start interrupt.
Set to 1 by user code to generate an interrupt when a start condition occurs.
Cleared to 0 by user code to disable interrupts when a start condition occurs.
LIN sync enable bit.
Set to 1 by user code to enable LHS functionality.
Cleared to 0 by user code to disable LHS functionality.
Edge counter clear bit.
Set to 1 by user code to clear the internal edge counters in the LHS peripheral.
Cleared automatically to 0 after a 15 μs delay.
LHS reset bit.
Set to 1 by user code to reset all LHS logic to default conditions.
Cleared automatically to 0 after a 15 μs delay.
LHSCON1
0x32
Read/write
The LHS control register is an 8-bit register that is used in conjunction with the LHSCON0 register to configure the LIN
mode of operation.
0xFFFF078C
Description
LIN stop edge count. These bits are set by user code to the number of falling or rising edges on which to stop the
internal LIN synchronization counter. The stop value of this counter can be read by user code via LHSVAL0. The type of
edge, either rising or falling, is configured by LHSCON0[7]. The default value of these bits is 0x3, which configures the
hardware to stop counting on the third falling edge. It should be noted that the first falling edge is considered to be the
falling edge at the start of the LIN break pulse.
LIN start edge count. These four bits are set by user code to the number of falling edges that must occur before the
internal LIN synchronization timer starts counting. The stop value of this counter can be read by user code via LHSVAL0.
The default value of these bits is 0x2, which configures the hardware to start counting on the second falling edge. Note
that the first falling edge is considered to be the falling edge at the start of the LIN break pulse.
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