ADUC7034BCPZ-RL Analog Devices Inc, ADUC7034BCPZ-RL Datasheet - Page 16

IC,Battery Management,LLCC,48PIN,PLASTIC

ADUC7034BCPZ-RL

Manufacturer Part Number
ADUC7034BCPZ-RL
Description
IC,Battery Management,LLCC,48PIN,PLASTIC
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC7xxxr
Datasheet

Specifications of ADUC7034BCPZ-RL

Core Processor
ARM7
Core Size
16/32-Bit
Speed
20.48MHz
Connectivity
LIN, SPI, UART/USART
Peripherals
POR, PSM, Temp Sensor, WDT
Number Of I /o
9
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 18 V
Data Converters
A/D 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 115°C
Package / Case
48-LFCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
ADuC7034
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 7. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8, 34, 35
9, 16, 23,
32, 38 to
40, 43, 45
17, 25, 26
10
Mnemonic
RESET
GPIO_5/IRQ1/RxD
GPIO_6/TxD
GPIO_7/IRQ4
GPIO_8/IRQ5
TCK
TDI
DGND
NC
NC
TDO
GPIO_5/IRQ1/RxD
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD SHOULD BE CONNECTED TO DGND.
Type
I
I/O
I/O
I/O
I/O
I
I
S
O
GPIO_7/IRQ4
GPIO_8/IRQ5
GPIO_6/TxD
1
RESET
NTRST
DGND
Description
Reset Input. Active low. This pin has an internal weak pull-up resistor to REG_DVDD and should
be left unconnected when not in use. For added security and robustness, it is recommended
that this pin be strapped via a resistor to REG_DVDD.
General-Purpose Digital IO 5/External Interrupt Request 1 (Active High)/Receive Data for UART
Serial Port. By default and after a power-on reset, this pin is configured as an input. The pin has
an internal weak pull-up resistor and should be left unconnected when not in use.
General-Purpose Digital IO 6/Transmit Data for UART Serial Port. By default and after a power-
on reset, this pin is configured as an input. The pin has an internal weak pull-up resistor and
should be left unconnected when not in use.
General-Purpose Digital IO 7/External Interrupt Request 4 (Active High). By default and after a
power-on reset, this pin is configured as an input. The pin has an internal weak pull-up resistor
and should be left unconnected when not in use.
General-Purpose Digital IO 8/External Interrupt Request 5 (Active High). By default and after
power-on reset, this pin is configured as an input. The pin has an internal weak pull-up resistor
and should be left unconnected when not in use.
JTAG Test Clock. This clock input pin is one of the standard 5-pin JTAG debug ports on the part.
TCK is an input pin only and has an internal weak pull-up resistor. This pin should be left
unconnected when not in use.
JTAG Test Data Input. This data input pin is one of the standard 5-pin JTAG debug ports on the
part. TDI is an input pin only and has an internal weak pull-up resistor. This pin should be left
unconnected when not in use.
Ground Reference for On-Chip Digital Circuits.
No Connect. Not internally connected and are reserved for possible future use. Therefore, do
not externally connect these pins. These pins can be grounded, if required.
No Connect. Internally connected and are reserved for possible future use. Therefore, do not
externally connect these pins. These pins can be grounded, if required.
JTAG Test Data Output. This data output pin is one of the standard 5-pin JTAG debug ports on
the part. TDO is an output pin only. At power-on, this output is disabled and pulled high via an
internal weak pull-up resistor. This pin should be left unconnected when not in use.
TCK
TDO
TMS
TDI
NC
10
12
11
1
2
3
4
5
6
7
8
9
Figure 7. Pin Configuration
PIN 1
INDICATOR
Rev. B | Page 16 of 136
ADuC7034
(Not to Scale)
TOP VIEW
36
35
34
33
32
31
30
29
28
27
26
25
XTAL1
DGND
DGND
REG_DVDD
NC
GPIO_4/ECLK
GPIO_3/MOSI
GPIO_2/MISO
GPIO_1/SCLK
GPIO_0/IRQ0/SS
NC
NC

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