ADUC7034BCPZ-RL Analog Devices Inc, ADUC7034BCPZ-RL Datasheet - Page 61

• Manufacturer Part Number: ADUC7034BCPZ-RL
• Description: IC,Battery Management,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7034BCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

POWER SUPPLY SUPPORT CIRCUITS
The ADuC7034 incorporates two on-chip low dropout (LDO)
regulators that are driven directly from the battery voltage to
generate a 2.6 V internal supply. This 2.6 V supply is then used
as the supply voltage for the ARM7 MCU and the peripherals,
including the on-chip precision analog circuits.
The digital LDO functions with two output capacitors (2.2 μF and
0.1 μF) in parallel on REG_DVDD, whereas the analog LDO
functions with an output capacitor (0.47 μF) on REG_AVDD.
The ESR of the output capacitor affects stability of the LDO
control loop. An ESR of 5 Ω or less for frequencies greater than
32 kHz is recommended to ensure the stability of the regulators.
In addition, the power-on reset (POR), power supply monitor
(PSM), and low voltage flag (LVF) functions are integrated to
ensure safe operation of the MCU, as well as continuous
monitoring of the battery power supply.
The POR circuit is designed to operate with a VDD power-on
time (from 0 V to 12 V) greater than 100 μs. It is, therefore,
recommended to carefully select external power supply decoupling
components to ensure that the VDD supply power-on time can
always be guaranteed to be greater than 100 μs, regardless of the
VBAT power-on conditions. The series resistor and decoupling
capacitor combination on VDD should be chosen to result in
an RC time constant of at least 100 μs, for example, 10 Ω and
10 μF, as shown in Figure 59.
(INTERNAL SIGNAL)
ENABLE_PSM
RESET_CORE
ENABLE_LVF
REG_DVDD
POR_TRIP
VDD
3V TYP
Figure 28. Typical Power-On Cycle
2.6V
12V
Rev. B | Page 61 of 136
20ms TYP
As shown in Figure 28, when the supply voltage on VDD
reaches a minimum operating voltage of 3 V, a POR signal
keeps the ARM core in a reset state for 20 ms. This ensures that
the regulated power supply voltage (REG_DVDD) applied to
the ARM core and its associated peripherals is greater than
the minimum operational voltage, thereby guaranteeing full
functionality. A POR flag is set in the RSTSTA MMR to indicate
that a POR reset event has occurred.
The ADuC7034 also features a power supply monitor (PSM)
function. When enabled through HVCFG0[3], the PSM
continuously monitors the voltage at the VDD pin. If the voltage
drops below 6.0 V typical, the PSM flag is automatically asserted
and can generate a system interrupt if the high voltage IRQ is
enabled via IRQ/FIQEN[16]. An example of this operation is
shown in Figure 28.
At voltages below the POR level voltage, an additional low
voltage flag can be enabled (HVCFG0[2]). This flag can be used
to indicate that the contents of the SRAM remain valid after a
reset event. The operation of the low voltage flag is shown in
Figure 28. When HVCFG0[2] is enabled, the status of this bit
can be monitored via HVMON[3]. If the HVCFG0[2] bit is set,
the SRAM contents are valid. If the HVCFG0[2] bit is cleared,
the SRAM contents may become corrupt.
PSM TRIP 6.0V TYP
POR TRIP 3.0V TYP
LVF TRIP 2.1V TYP
ADuC7034