ADUC7034BCPZ-RL Analog Devices Inc, ADUC7034BCPZ-RL Datasheet - Page 117

• Manufacturer Part Number: ADUC7034BCPZ-RL
• Description: IC,Battery Management,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7034BCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LIN (LOCAL INTERCONNECT NETWORK) INTERFACE
The ADuC7034 features high voltage physical interfaces
between the ARM7 MCU core and an external LIN bus. The
LIN interface operates as a slave only interface, operating from
1 kBaud to 20 kBaud, and it is compatible with the LIN 2.0
standard. The pull-up resistor required for a slave node is on
chip, reducing the need for external circuitry. The LIN protocol
is emulated using the on-chip UART, an IRQ, a dedicated LIN
timer, and the high voltage transceiver (also incorporated on
chip) as shown in Figure 45. The LIN is clocked from the low
power oscillator for the break timer, and a 5 MHz output from
the PLL is used for the synchronous byte timing.
GPSDAT[21]
GP2DAT[29]
131kHz
LHS INTERRUPT
5MHz
GPIO12
IRQEN[7]
AND
HARDWARE
LHSVAL0
LHSVAL1
UART
LHS
RxD ENABLE
LHSCON0[8]
GP2CON[20]
FUNCTION
RxD
TxD
SELECT
GPIO12
INTERRUPT
LOGIC
LHS
DISABLE
OUTPUT
Figure 45. LIN I/O Block Diagram
SHORT-CIRCUIT
HVCFG0[1:0]
LIN MODE
HVCFG1[2]
CONTROL
FOUR LIN
INTERRUPT
SOURCES:
BREAK LHSSTA[0]
START LHSSTA[1]
STOP LHSSTA[2]
BREAK
ERROR LHSSTA[4]
Rev. B | Page 117 of 136
INPUT
VOLTAGE
THRESHOLD
REFERENCE
BPF
TRIP REFERENCE
SHORT-CIRCUIT
INTERNAL
LIN MMR DESCRIPTION
The LIN hardware synchronization (LHS) functionality is con-
trolled through five MMRs. The function of each MMR is as
follows:
•
•
•
•
•
LHSSTA: LHS status register. This MMR contains information
flags that describe the current status on the interface.
LHSCON0: LHS Control Register 0. This MMR controls
the configuration of the LHS timer.
LHSCON1: LHS start and stop edge control register. This
MMR dictates on which edge of the LIN synchronization byte
the LHS starts/stops counting.
LHSVAL0: LHS synchronization 16-bit timer. This MMR is
controlled by LHSCON0.
LHSVAL1: LHS break timer register.
VDD
INTERNAL
SHORT-CIRCUIT
SENSE
RESISTOR
OVERVOLTAGE
PROTECTION
LIN ENABLE
(INTERNAL
HVCFG0[5]
PULL-UP)
EXTERNAL
LIN PIN
IO_VSS
SCR
VDD
MASTER ECU
PROTECTION
DIODE
MASTER ECU
PULL-UP
C
LOAD
ADuC7034