ADUC7034BCPZ-RL Analog Devices Inc, ADUC7034BCPZ-RL Datasheet - Page 56

• Manufacturer Part Number: ADUC7034BCPZ-RL
• Description: IC,Battery Management,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7034BCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7034
ADC Low Power Plus Mode
In low power plus mode, the I-ADC channel is enabled in a
mode almost identical to low power mode (ADCMDE[4:3]).
However, in this mode, the I-ADC gain is fixed at 512 and the
ADC consumes an additional 200 μA (approximately) to yield
improved noise performance relative to the low power mode
setting.
All ADC peripheral functions (result counter, digital comparator,
and accumulator) described in the ADC Normal Power Mode
section can also be enabled in low power plus mode.
As in low power mode, only the I-ADC is configured to run at a
low update rate and to continuously monitor battery current.
The MCU is in power-down mode and wakes up when the I-ADC
interrupts the MCU, which occurs after the I-ADC detects a
current conversion result that exceeds a preprogrammed threshold,
a setpoint, or a set number of conversions.
It is also possible to select either the ADC precision voltage
reference or the ADC low power mode voltage reference via
ADCMDE[5].
ADC COMPARATOR AND ACCUMULATOR
The incorporation of comparator logic on the I-ADC allows the
I-ADC result to generate an interrupt after a predefined number of
conversions has elapsed or a programmable threshold value has
been exceeded.
Every I-ADC result can be compared with a preset threshold
level (ADC0TH) that is set via ADCCFG[4:3]. In this case, an
MCU interrupt is generated if the absolute (sign independent)
value of the ADC result is greater than the preprogrammed
comparator threshold level. Alternatively, as an extended function
of the comparator, user code can configure a threshold counter
(ADC0THV) to monitor the number of I-ADC results that occur
above or below the preset threshold level. In this case, an ADC
interrupt is generated when the threshold counter reaches a
preset value that is set via ADC0TCL.
By also incorporating a 32-bit accumulator (ADC0ACC) function,
which can be configured via ADCCFG[6:5], the I-ADC can add
or subtract multiple I-ADC sample results. User code can read
the accumulated value directly from ADC0ACC without any
further software processing.
ADC SINC3 DIGITAL FILTER RESPONSE
The overall frequency response on all ADuC7034 ADCs is
dominated by the low-pass filter response of the on-chip sinc3
digital filters. The sinc3 filters are used to decimate the ADC
Σ-Δ modulator output data bit stream to generate a valid 16-bit
data result. The digital filter response is identical for all ADCs
and is configured via the 16-bit ADC filter register (ADCFLT).
This register determines the overall throughput rate of the ADCs.
The noise resolution of the ADCs is determined by the pro-
grammed ADC throughput rate. In the case of the current
Rev. B | Page 56 of 136
channel ADC, the noise resolution is determined by throughput
rate and selected gain.
The overall frequency response and the ADC throughput is
dominated by the configuration of the sinc3 filter decimation
factor (SF) bits (ADCFLT[6:0]) and the averaging factor (AF)
bits (ADCFLT[13:8]). Due to limitations on the digital filter
internal data path, there are some limitations on the allowable
combinations of SF and AF that can be used to generate a
required ADC output rate. This restriction limits the minimum
ADC update to 4 Hz in normal power mode and to 1 Hz in low
power mode. The calculation of the ADC throughput rate is
detailed in the ADCFLT MMR bit designations table (Table 38),
and the restrictions on allowable combinations of AF and SF
values are outlined in Table 40.
By default, ADCFLT = 0x0007 configures the ADCs for a
throughput of 1 kHz with all other filtering options (chop,
running average, averaging factor, and sinc3 modify) disabled.
A typical filter response based on this default configuration is
shown in Figure 21.
In addition, a sinc3 modify bit (ADCFLT[7]) is available in the
ADCFLT register. This bit is set by user code and modifies the
standard sinc3 frequency response to increase the filter stop-
band rejection by approximately 5 dB. This is achieved by inserting
a second notch at the location determined by
where f
There is a slight increase in ADC noise if the sinc3 modify bit is
active. Figure 22 shows the modified 1 kHz filter response when
the sinc3 modify bit is active. The new notch is clearly visible at
1.33 kHz, as is the improvement in stop-band rejection when
compared with the standard 1 kHz response.
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
f
0
NOTCH2
0
NOTCH
Figure 21. Typical Digital Filter Response at f
500
= 1.333 × f
is the location of the first notch in the response.
1000 1500 2000 2500 3000 3500 4000 4500 5000
NOTCH
FREQUENCY (kHz)
(ADCFLT = 0x0007)
ADC
= 1 kHz