ADUC7034BCPZ-RL Analog Devices Inc, ADUC7034BCPZ-RL Datasheet - Page 29

• Manufacturer Part Number: ADUC7034BCPZ-RL
• Description: IC,Battery Management,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7034BCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Temporary Protection
Temporary protection can be set and removed by writing
directly into the FEE0HID MMR. This register is volatile and,
therefore, protection is only in place for as long as the part
remains powered on. The protection setting is not reloaded
after a power cycle.
Keyed Permanent Protection
Keyed permanent protection can be set via FEE0PRO to lock
the protection configuration. The software key used at the start
of the required FEE0PRO write sequence is saved one time only
and must be used for any subsequent access of the FEE0HID or
FEE0PRO MMRs. A mass erase sets the software protection key
back to 0xFFFF but also erases the entire user code space.
Permanent Protection
Permanent protection can be set via FEE0PRO, similar to how
keyed permanent protection is set, with the only difference
being that the software key used is 0xDEADDEAD. When the
FEE0PRO write sequence is saved, only a mass erase sets the
software protection key back to 0xFFFFFFFF. This also erases
the entire user code space.
Sequence to Write the Software Protection Key and Set
Permanent Protection
1.
2.
3.
4.
To remove or modify the protection, the same sequence can be
used with a modified value of FEE0PRO.
The previous sequence for writing the key and setting perma-
nent protection is illustrated in the following example, this
protects writing Page 4 and Page 5 of the Flash/EE:
Int a = FEE0STA;
is cleared
FEE0PRO = 0xFFFFFFFB;
and Page 5
FEE0ADR = 0x66BB;
value (Bits[31:16])
FEE0DAT = 0xAA55;
value (Bits[15:0])
FEE0MOD = 0x0048
sequence
FEE0CON = 0x0C;
command
while (FEE0STA & 0x04){} // Wait for
command to finish
Write in FEE0PRO corresponding to the pages to be
protected.
Write the new (user-defined) 32-bit software protection
key in FEE0ADR (Bits[31:16]) and FEE0DAT (Bits[15:0]).
Write 10 in FEE0MOD (Bits[6:5]) and set FEE0MOD (Bit 3).
Run the protect command (Code 0x0C) in FEE0CON.
// Ensure FEE0STA
// Protect Page 4
// 32-bit key
// 32-bit key
// Lock security
// Write key
Rev. B | Page 29 of 136
FLASH/EE MEMORY RELIABILITY
The Flash/EE memory array on the part is fully qualified for
two key Flash/EE memory characteristics: Flash/EE memory
cycling endurance and Flash/EE memory data retention.
Endurance quantifies the ability of the Flash/EE memory to be
cycled through many program, read, and erase cycles. A single
endurance cycle is composed of four independent, sequential
events, defined as
•
•
•
•
In reliability qualification, every halfword (16 bits wide) location of
the three pages (top, middle, and bottom) in the Flash/EE memory
is cycled 10,000 times from 0x0000 to 0xFFFF. As indicated in
Table 1, the Flash/EE memory endurance qualification of the
part is carried out in accordance with JEDEC Retention Lifetime
Specification A117. The results allow the specification of a
minimum endurance figure over supply and temperature of
10,000 cycles.
Retention quantifies the ability of the Flash/EE memory to
retain its programmed data over time. Again, the part is
qualified in accordance with the formal JEDEC Retention
Lifetime Specification A117 at a specific junction temperature
(T
Flash/EE memory is cycled to its specified endurance limit,
described previously, before data retention is characterized.
This means that the Flash/EE memory is guaranteed to retain
its data for the fully specified retention lifetime every time the
Flash/EE memory is reprogrammed. In addition, note that the
retention lifetime, based on an activation energy of 0.6 eV, derates
with T
J
= 85°C). As part of this qualification procedure, the
Initial page erase sequence
Read/verify sequence
Byte program sequence
Second read/verify sequence
J
as shown in Figure 14.
600
450
300
150
0
25
Figure 14. Flash/EE Memory Data Retention
40
JUNCTION TEMPERATURE (°C)
55
70
85
100
115
ADuC7034
130
145