ADUC7034BCPZ-RL Analog Devices Inc, ADUC7034BCPZ-RL Datasheet - Page 38

• Manufacturer Part Number: ADUC7034BCPZ-RL
• Description: IC,Battery Management,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7034BCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7034
Table 26. STI Base Address = 0xFFFF0880
Address
0x0880
0x0884
0x0888
0x088C
0x0890
0x0894
Table 27. SPI Base Address = 0xFFFF0A00
Address
0x0A00
0x0A04
0x0A08
0x0A0C
0x0A10
Table 28. GPIO Base Address = 0xFFFF0D00
Address
0x0D00
0x0D04
0x0D08
0x0D20
0x0D24
0x0D28
0x0D30
0x0D34
0x0D38
0x0D40
0x0D44
0x0D48
1
Depends on the level on the external GPIO pins.
Name
STIKEY0
STICON
STIKEY1
STIDAT0
STIDAT1
STIDAT2
Name
GP0CON
GP1CON
GP2CON
GP0DAT
GP0SET
GP0CLR
GP1DAT
GP1SET
GP1CLR
GP2DAT
GP2SET
GP2CLR
Name
SPISTA
SPIRX
SPITX
SPIDIV
SPICON
1
1
1
Byte
4
2
2
2
2
4
Byte
1
1
1
1
2
Byte
4
4
4
4
4
4
4
4
4
4
4
4
Access
Type
W
RW
W
RW
RW
RW
R
R
W
RW
RW
Access Type
Access
Type
RW
RW
RW
RW
W
W
RW
W
W
RW
W
W
Default Value
N/A
0x0000
N/A
0x0000
0x0000
0x0000
Default Value
0x11100000
0x10000000
0x01000000
0x000000XX
0x000000XX
0x000000XX
Default Value
0x00
0x00
0x1B
0x00
Rev. B | Page 38 of 136
Description
STICON prewrite key. See the Serial Test Interface Key0 Register section.
Serial test interface control MMR. See the Serial Test Interface Control Register
section and Table 90.
STICON postwrite key. See the Serial Test Interface Key1 Register section and
Table 90.
STI Data MMR 0. See the Serial Test Interface Data0 Register section.
STI Data MMR 1. See the Serial Test Interface Data1 Register section.
STI Data MMR 2. See the Serial Test Interface Data2 Register section.
Description
GPIO Port0 control MMR. See the GPIO Port0 Control Register section and
Table 58.
GPIO Port1 control MMR. See the GPIO Port1 Control Register section and
Table 59.
GPIO Port2 control MMR. See the GPIO Port2 Control Register section and
Table 60.
GPIO Port0 data control MMR. See the GPIO Port0 Data Register section and
Table 61.
GPIO Port0 data set MMR. See the GPIO Port0 Set Register section and
Table 64.
GPIO Port0 data clear MMR. See the GPIO Port0 Clear Register section and
Table 67.
GPIO Port1 data control MMR. See the GPIO Port1 Data Register section and
Table 62.
GPIO Port1 data set MMR. See the GPIO Port1 Set Register section and
Table 65.
GPIO Port1 data clear MMR. See the GPIO Port1 Clear Register section and
Table 68.
GPIO Port2 Data Control MMR. See the GPIO Port2 Data Register section and
Table 63.
GPIO Port2 data set MMR. See the GPIO Port2 Set Register section and
Table 66.
GPIO Port2 data clear MMR. See the GPIO Port2 Clear Register section and
Table 69.
Description
SPI status MMR. See the SPI Status Register section and Table 89.
SPI receive MMR. See the SPI Receive Register section.
SPI transmit MMR. See the SPI Transmit Register section.
SPI baud rate select MMR. See the SPI Divider Register section.
SPI control MMR. See the SPI Control Register section and Table 88.