ADUC7034BCPZ-RL Analog Devices Inc, ADUC7034BCPZ-RL Datasheet - Page 47

• Manufacturer Part Number: ADUC7034BCPZ-RL
• Description: IC,Battery Management,LLCC,48PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7034BCPZ-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 20.48MHz
• Connectivity: LIN, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 9
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 18 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 115°C
• Package / Case: 48-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Current Channel ADC Control Register
Name:
Address:
Default Value:
Access:
Function:
Note:
Table 36. ADC0CON MMR Bit Designations
Bit
15
14 to 13
12 to 10
9
8
7 to 6
5 to 4
3 to 0
ADC0CON
0xFFFF050C
0x0000
Read/write
The current channel ADC control MMR is a 16-bit register that is used to configure the I-ADC.
If the current ADC is reconfigured via ADC0CON, the voltage ADC and temperature ADC are also reset.
Description
Current channel ADC enable.
Set to 1 by user code to enable the I-ADC.
Clearing this bit to 0 powers down the I-ADC and resets the respective ADC ready bit in the ADCSTA MMR to 0.
IIN current source enable.
00 = disables current sources.
01 = enables 50 μA current source on IIN+.
10 = enables 50 μA current source on IIN−.
11 = enables 50 μA current source on both IIN− and IIN+.
Not used. These bits are reserved for future functionality and should be written as 0.
Current channel ADC output coding.
Set to 1 by user code to configure I-ADC output coding as unipolar.
Cleared to 0 by user code to configure I-ADC output coding as twos complement.
Not used. This bit is reserved for future functionality and should be written as 0.
Current channel ADC inputs select.
00 = IIN+ and IIN− are selected.
01 = IIN− and IIN− are selected. Diagnostic, internal short configuration.
10 = VREF/136 and 0 V are selected. Diagnostic, test voltage for gain settings ≤ 128. If the reference REG_AVDD and
AGND divided by 2 is selected, REG_AVDD is used for VREF. This leads to ADC0DAT being scaled by 2.
11 = not defined.
Current channel ADC reference select.
00 = internal 1.2 V precision reference is selected. In ADC low power mode, the voltage reference selection is controlled
by ADCMDE[5].
01 = external reference inputs VREF and GND_SW are selected.
10 = external reference inputs divided by 2 (that is, VREF and GND_SW divided by 2) are selected, which allows an
external reference up to REG_AVDD.
11 = the reference REG_AVDD and AGND divided by 2 is selected.
Current channel ADC gain select. The nominal I-ADC full-scale input voltage is VREF/gain.
0000 = I-ADC gain of 1.
0001 = I-ADC gain of 2.
0010 = I-ADC gain of 4.
0011 = I-ADC gain of 8.
0100 = I-ADC gain of 16.
0101 = I-ADC gain of 32.
0110 = I-ADC gain of 64.
0111 = I-ADC gain of 128.
1000 = I-ADC gain of 256.
1001 = I-ADC gain of 512.
1010 = I-ADC gain is undefined.
1011 = I-ADC gain is undefined.
1100 = I-ADC gain is undefined.
1101 = I-ADC gain is undefined.
1110 = I-ADC gain is undefined.
1111 = I-ADC gain is undefined.
Rev. B | Page 47 of 136
ADuC7034