ALXD800EEXJCVD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJCVD C3 Datasheet - Page 115

• Manufacturer Part Number: ALXD800EEXJCVD C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJCVD C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

CPU Core Register Descriptions
5.5.2.9
MSR Address
Type
Reset Value
IF_CONFG_MSR controls the operation of the Instruction Fetch (IF). The Level-0 COF cache (Change of Flow (COF)
cache), L1 COF cache, return stack, and power saving mode may be turned on or off. The WRMSR instruction can access
IF_CONFIG MSR at any time. Devices external to the CPU should issue writes to IF_CONFIG MSR only if the CPU is sus-
pended or stalled.
AMD Geode™ LX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:48
43:41
40:37
35:32
31:29
RSVD
Bit
47
46
45
44
36
Instruction Fetch Configuration MSR (IF_CONFIG_MSR)
Name
RSVD
BETD
BIVD
LSNPD
PSNPD
RSVD
BSP
RSVD
W_DIS
RSVD
RSVD
00001100h
R/W
00000000_00005051h
RSVD
Description
Reserved.
Branch Tree Messaging (BTM) Exception Type. Allow the BTM stream to contain
exception type records.
0: Enable. (Default)
1: Disable.
Branch Tree Messaging Interrupt Vector. Allow the BTM stream to contain interrupt
vector records.
0: Enable. (Default)
1: Disable.
Linear Snooping.
0: Enable. (Default)
1: Disable.
Physical Snooping.
0: Enable. (Default)
1: Disable.
Reserved.
Branch Tree Messaging Sync Period. Specifies the maximum period between BTM
synchronization records. If BSP is non-zero, the IF will insert a synchronization record
into the BTM stream whenever it sees a series of 32*BSP non-synchronization records.
(Default = 0)
Reserved.
Branch Target Buffer (BTB) Way. Each bit is used to disable one Way of the BTB. Bit
32 = Way 0, bit 33 = Way 1, bit 34 = Way 2, and bit 35 = Way 3.
0: Enable Way. (Default)
1: Disable Way.
Reserved.
RSVD
IF_CONFIG_MSR Bit Descriptions
IF_CONFIG_MSR Register Map
RSVD
RSVD
9
8
33234H
7
BSP
6
5
4
3
W_DIS
2
1
115
0