ALXD800EEXJCVD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJCVD C3 Datasheet - Page 230

• Manufacturer Part Number: ALXD800EEXJCVD C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJCVD C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

230
63:56
55:53
52:51
47:42
39:34
30:28
27:24
23:20
18:16
14:12
Bit
50
49
48
41
40
33
32
31
19
15
Name
STALE_REQ
RSVD
XOR_BIT_SEL
XOR_MB0
XOR_BA1
XOR_BA0
RSVD
TRUNC_DIS
REORDER_DIS
RSVD
HOI_LOI
RSVD
THZ_DLY
CAS_LAT
ACT2ACTREF
ACT2PRE
RSVD
PRE2ACT
RSVD
ACT2CMD
33234H
Description
GLIU Max Stale Request Count. Non-high priority requests (PRI = 0) are made high-pri-
ority requests when the request is not serviced within max stale request count clocks.
(Default = 18h)
Reserved.
XOR Bit Select. Selects which upper GLIU address bit to XOR with MB0, BA1 or BA0
(see "Auto Low Order Interleaving" on page 212). Only applies to LOI mode. (Default =
00).
XOR MB0 Enable. Enables XORing of module bank select MB0 with upper GLIU
address bit selected by XOR_BIT_SEL (bits [52:51]). (Default = 0, Disabled)
XOR BA1 Enable. Enables XORing of component bank select BA1 with upper GLIU
address bit selected by XOR_BIT_SEL (bits [52:51]). (Default = 0, Disabled)
XOR BA0 Enable. Enables XORing of component bank select BA0 with upper GLIU
address bit selected by XOR_BIT_SEL (bits [52:51]). (Default = 0, Disabled)
Reserved.
Burst Truncate Disable. Disables truncation of read/write bursts. This disable reduces
performance and should only be used during debug. (Default = 0, bursts enabled)
Reorder Disable. Disables the reordering of requests. This bit must be set to 1.
Reserved.
High / Low Order Interleave Select (HOI / LOI). Selects the address interleaving mode.
HOI uses fixed upper address bits to map the GLIU address to a component bank. LOI
uses variable lower address bits depending on page size, number of module banks, and
number of component banks of the DIMMs, plus an option to XOR with upper address
bits.
1: HOI.
0: LOI. (Default)
Reserved.
tHZ Delay. Add 1 extra clock on read-to-write turnarounds to satisfy DRAM parameter
t
Read CAS Latency. Number of clock delays between Read command and Data valid.
CAS Latency:
000: RSVD
001: RSVD
ACT to ACT/REF Period. tRC. Minimum number of SDRAM clocks between ACTIVE
and ACTIVE/AUTO REFRESH commands. (Default = 8h)
ACT to PRE Period. tRAS. Minimum number of clocks from ACT to PRE commands on
the same component bank. (Default = 7h)
Reserved.
Pre to Act Period. tRP. Minimum number of SDRAM clocks between PRE and ACT com-
mands. (Default = 011)
Reserved.
Delay Time from Act To read/WRITE. tRCD. Minimum number of SDRAM clocks
between ACT and READ/WRITE commands. (6..2 valid). (Default = 011)
00: ADDR[18] 01: ADDR[19] 10: ADDR[20] 11: ADDR[21]
HZ
for higher frequencies. (Default = 0)
MC_CF8F_DATA Bit Descriptions
010: 2 (Default)
011: 3
100: 4
101: 1.5
GeodeLink™ Memory Controller Register Descriptions
AMD Geode™ LX Processors Data Book
110: 2.5
111: 3.5