ALXD800EEXJCVD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJCVD C3 Datasheet - Page 185

• Manufacturer Part Number: ALXD800EEXJCVD C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJCVD C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

CPU Core Register Descriptions
5.5.2.91
MSR Address
Type
Reset Value
5.5.2.92 MSR Lock MSR (MSR_LOCK_MSR)
MSR Address
Type
Reset Value
AMD Geode™ LX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:0
63:1
Bit
Bit
0
Reserved Status MSR (RSVD_STS_MSR)
Name
RSVD (RO)
Name
RSVD
MSR_LOCK
00001904h
RO
00000000_00000000h
00001908h
R/W
00000000_00000000h
Description
Reserved (Read Only). Reads back as 0.
Description
Reserved. Write as read
Lock MSRs. The CPU Core MSRs above 0xFFF (with the exception of the MSR_LOCK
register itself) are locked when this bit reads back as 1. To unlock these MSRs, write the
value 45524F434C494156h to this register. Writing any other value locks the MSRs.
The lock only affects software access via the WRMSR and RDMSR instructions when the
processor is NOT in SMM or DMM mode. MSRs are always writable and readable from
the GLBus and when the processor is in SMM or DMM mode regardless of the state of
the LOCK bit.
Note that a write or read to a locked MSR register causes a protection exception in the
pipeline.
When MSRs are locked, no GLBus MSR transactions are generated (GLBus MSR
addresses are above 3FFFh).
MSR_LOCK_MSR Bit Descriptions
RSVD_STS_MSR Bit Descriptions
MSR_LOCK_MSR Register Map
RSVD
RSVD
9
8
33234H
7
6
5
4
3
2
1
185
0