ALXD800EEXJCVD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJCVD C3 Datasheet - Page 127

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ALXD800EEXJCVD C3

Manufacturer Part Number
ALXD800EEXJCVD C3
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet

Specifications of ALXD800EEXJCVD C3

Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
CPU Core Register Descriptions
5.5.2.18 XC Microcode Address MSR (XC_UADDR_MSR)
MSR Address
Type
Reset Value
5.5.2.19 ID Configuration MSR (ID_CONFIG_MSR)
MSR Address
Type
Reset Value
AMD Geode™ LX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:60
59:48
47:36
35:24
23:12
63:3
11:0
Bit
Bit
RSVD
2
1
0
UADDR2[7:0]
Name
RSVD (RO)
GPF_TR
INV_3DNOW
SERIAL
Name
RSVD
UADDR4
UADDR3
UADDR2
UADDR1
UADDR0
00001213h
RO
00000000_00000000h
00001250h
R/W
00000000_00000002h
Description
Reserved (Read Only).
General Protection Faults on Test Register Accesses. Generate general protection
faults on accesses to Test Registers.
0: Disable. (Default)
1: Enable.
Inverse 3DNow!™. Inverse AMD 3DNow!™ instructions PFRCPV and RFRSQRTV.
0: Disable.
1: Enable. (Default)
Serialize. Serialize the CPU integer pipeline by only allowing one instruction in the pipe-
line at a time.
0: Integer pipeline is not serialized. (Default)
1: Integer pipeline is serialized.
Description
Reserved.
Microcode Address for Exception 4.
Microcode Address for Exception 3.
Microcode Address for Exception 2.
Microcode Address for Exception 1.
Microcode Address for Exception 0. Most recent exception.
UADDR4
XC_UADDR_MSR Bit Descriptions
ID_CONFIG_MSR Bit Descriptions
ID_CONFIG_MSR Register Map
XC_UADDR_MSR Register Map
UADDR1
RSVD
RSVD
UADDR3
9
9
8
8
33234H
7
7
UADDR0
6
6
5
5
4
4
UADDR2[11:8]
3
3
2
2
1
1
127
0
0

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