ALXD800EEXJCVD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJCVD C3 Datasheet - Page 301
![no-image](/images/manufacturer_photos/0/0/44/amd__advanced_micro_devices__sml.jpg)
ALXD800EEXJCVD C3
Manufacturer Part Number
ALXD800EEXJCVD C3
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.ALXD800EEXJCVD_C3.pdf
(680 pages)
Specifications of ALXD800EEXJCVD C3
Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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Display Controller Register Descriptions
AMD Geode™ LX Processors Data Book
Timing Registers
Cursor Position and Count Status Registers
Palette Access and FIFO Diagnostic Registers
Video Downscaling Registers
GLIU0 Control Registers
Memory
Offset
02Ch
05Ch
06Ch
07Ch
020h
024h
028h
030h
034h
038h
040h
044h
048h
050h
054h
058h
060h
064h
070h
074h
078h
080h
084h
088h
DC
Type
Table 6-47. DC Configuration Control Register Summary (Continued)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
Register Name
DC Video Y Buffer Start Address Offset
(DC_VID_Y_ST_OFFSET)
DC Video U Buffer Start Address Offset
(DC_VID_U_ST_OFFSET)
DC Video V Buffer Start Address Offset
(DC_VID_V_ST_OFFSET)
DC Dirty/Valid Region Top (DC_DV_TOP)
DC Line Size (DC_LINE_SIZE)
DC Graphics Pitch (DC_GFX_PITCH)
DC Video YUV Pitch (DC_VID_YUV_PITCH)
DC Horizontal and Total Timing
(DC_H_ACTIVE_TIMING)
DC CRT Horizontal Blanking Timing
(DC_H_BLANK_TIMING)
DC CRT Horizontal Sync Timing
(DC_H_SYNC_TIMING)
DC Vertical and Total Timing
(DC_V_ACTIVE_TIMING)
DC CRT Vertical Blank Timing
(DC_V_BLANK_TIMING)
DC CRT Vertical Sync Timing
(DC_V_SYNC_TIMING)
DC Frame Buffer Active Region Register
(DC_FB_ACTIVE)
DC Cursor X Position (DC_CURSOR_X)
DC Cursor Y Position (DC_CURSOR_Y)
DC Line Count/Status (DC_LINE_CNT/STATUS)
DC Palette Address (DC_PAL_ADDRESS)
DC Palette Data (DC_PAL_DATA)
DC Display FIFO Diagnostic (DC_DFIFO_DIAG)
DC Compression FIFO Diagnostic
(DC_CFIFO_DIAG)
DC Video Downscaling Delta (DC_VID_DS_DELTA)
DC GLIU0 Memory Offset
(DC_GLIU0_MEM_OFFSET)
DC Dirty/Valid RAM Control (DC_DV_CTL)
Reset Value
00000000h
00000000h
00000000h
00000000h
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33234H
Reference
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