ALXD800EEXJCVD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJCVD C3 Datasheet - Page 572

• Manufacturer Part Number: ALXD800EEXJCVD C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJCVD C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.16
All GeodeLink™ PCI Bridge (GLPCI) registers are Model
Specific Registers (MSRs) and are accessed via the
RDMSR and WRMSR instructions.
The registers associated with the GLPCI are the Standard
GeodeLink Device (GLD) MSRs and GLPCI Specific
MSRs. Table 6-91 and Table 6-92 are register summary
572
5000201Ah
5000201Bh
5000201Ch
50002000h
50002001h
50002002h
50002003h
50002004h
50002005h
50002010h
50002011h
50002012h
50002013h
50002014h
50002015h
50002016h
50002017h
50002018h
50002019h
Address
Address
MSR
MSR
GeodeLink™ PCI Bridge Register Descriptions
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
33234H
Table 6-91. Standard GeodeLink™ Device MSRs Summary
Register Name
GLD Capabilities MSR (GLD_MSR_CAP)
GLD Master Configuration MSR
(GLD_MSR_CONFIG)
GLD SMI MSR (GLD_MSR_SMI)
GLD Error MSR (GLD_MSR_ERROR)
GLD Power Management MSR
(GLD_MSR_PM)
GLD Diagnostic MSR (GLD_MSR_DIAG)
Register Name
GLPCI Global Control (GLPCI_CTRL)
GLPCI Arbiter Control (GLPCI_ARB)
GLPCI VPH / PCI Configuration Cycle Con-
trol (GLPCI_PBUS)
GLPCI Debug Packet Configuration
(GLPCI_DEBUG)
GLPCI Fixed Region Enables
(GLPCI_REN)
GLPCI Fixed Region Configuration A0-BF
(GLPCI_A0)
GLPCI Fixed Region Configuration C0-DF
(GLPCI_C0)
GLPCI Fixed Region Configuration E0-FF
(GLPCI_E0)
GLPCI Memory Region 0 Configuration
(GLPCI_R0)
GLPCI Memory Region 1 Configuration
(GLPCI_R1)
GLPCI Memory Region 2 Configuration
(GLPCI_R2)
GLCPI Memory Region 3 Configuration
(GLPCI_R3)
GLCPI Memory Region 4 Configuration
(GLPCI_R4)
Table 6-92. GLPCI Specific Registers Summary
tables that include reset values and page references where
the bit descriptions are provided.
The MSR address is derived from the perspective of the
CPU Core. See Section 4.1 "MSR Set" on page 45 for
more detail on MSR addressing.
GeodeLink™ PCI Bridge Register Descriptions
00FF0000_00000000h
00000000_00000000h
00000000_0000003Fh
00000000_0000003Fh
00000000_00000015h
00000000_00000000h
44000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_001054xxh
AMD Geode™ LX Processors Data Book
Reset Value
Reset Value
Reference
Reference
Page 574
Page 574
Page 575
Page 576
Page 577
Page 577
Page 578
Page 581
Page 584
Page 584
Page 584
Page 585
Page 586
Page 587
Page 588
Page 589
Page 590
Page 591
Page 592