ALXD800EEXJCVD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJCVD C3 Datasheet - Page 193

• Manufacturer Part Number: ALXD800EEXJCVD C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJCVD C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

CPU Core Register Descriptions
5.5.2.103 Power Mode MSR (PMODE_MSR)
MSR Address
Type
Reset Value
This MSR enables some modules to turn their clocks off when they are idle to save power. Most of these bits are off by
default. It is recommended that they be set by BIOS.
AMD Geode™ LX Processors Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:19
Bit
18
17
16
9
8
1
0
Name
RSVD
IRS_IF
IRS_IMTAG
IRS_IMDATA
FPU_EX
FPU_FP
BCL2_MSR
BCL2_GATED
00001930h
R/W
00000000_00000300h
RSVD
Description
Reserved.
Reserved, Instruction Fetch. Reserved for possible future clock gating of IF.
(Default = 0)
Reserved, Instruction Memory Subsystem. Reserved for possible future clock gating
IM tag. (Default = 0)
Instruction Memory Subsystem Data. When bit is set, IM may turn off the clock when
IM_DATA is idle. (Default = 0)
FPU EX. When bit is set, FPU may turn off the clock to FPU Region 1 when FP_EX is
idle. (Default = 1)
FPU_FP. When bit is set, FPU may turn off the clock to FPU Region 2 when FPU is idle.
(Default = 1)
BCL2 MSR. When bit is set, BCL2 may turn off the clock to BC Region 1 when
BCL2_MSR is idle. (Default = 0)
BCL2 Gated. When bit is set, BCL2 may turn off the clock to BC Region 2 when BCL2 is
idle. (Default = 0)
PMODE_MSR Bit Descriptions
PMODE_MSR Register Map
RSVD
RSVD
9
8
33234H
7
6
RSVD
5
4
3
2
1
193
0