ALXD800EEXJCVD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJCVD C3 Datasheet - Page 352
ALXD800EEXJCVD C3
Manufacturer Part Number
ALXD800EEXJCVD C3
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.ALXD800EEXJCVD_C3.pdf
(680 pages)
Specifications of ALXD800EEXJCVD C3
Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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6.6.14.2 DC Even Field Video U Start Address Offset (DC_VID_EVEN_U_ST_OFFSET)
DC Memory Offset 0DCh
Type
Reset Value
Settings written to this register do not take effect until the start of the next even interlaced field.
6.6.14.3 DC Even Field Video V Start Address Offset (DC_VID_EVEN_V_ST_OFFSET)
DC Memory Offset 0E0h
Type
Reset Value
Settings written to this register do not take effect until the start of the next even interlaced field.
352
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31:28
31:28
27:0
27:0
Bit
Bit
RSVD
RSVD
Name
RSVD
OFFSET
Name
RSVD
OFFSET
R/W
xxxxxxxxh
R/W
xxxxxxxxh
33234H
Description
Reserved. Set to 0.
Video U Even Buffer Start Offset. This value represents the starting location for Video
U Buffer for even fields when interlacing is enabled (DC Memory Offset 094h[11] = 1)
and YUV 4:2:0 mode is selected (DC Memory Offset 004h[20] = 1). The lower five bits
should always be programmed as zero so that the start offset is aligned to a 32-byte
boundary.
Description
Reserved. Set to 0.
Video V Even Buffer Start Offset. This value represents the starting location for Video
V Buffer for even fields when interlacing is enabled (DC Memory Offset 094h[11] = 1) and
YUV 4:2:0 is selected (DC Memory Offset 004h[20] = 1). The lower five bits should
always be programmed as zero so that the start offset is aligned to a 32-byte boundary.
DC_VID_EVEN_U_ST_OFFSET Bit Descriptions
DC_VID_EVEN_V_ST_OFFSET Bit Descriptions
DC_VID_EVEN_U_ST_OFFSET Register Map
DC_VID_EVEN_V_ST_OFFSET Register Map
OFFSET
OFFSET
Display Controller Register Descriptions
AMD Geode™ LX Processors Data Book
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
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