ALXD800EEXJCVD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJCVD C3 Datasheet - Page 661

• Manufacturer Part Number: ALXD800EEXJCVD C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJCVD C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Instruction Set
AMD Geode™ LX Processors Data Book
PADDUSW Add Unsigned Word with Saturation
PADDW Packed Add Word with Wrap-Around
PAND Bitwise Logical AND
PANDN Bitwise Logical AND NOT
PAVGB Packed Average of Unsigned Byte
PAVGW Packed Average of Unsigned Word
MMX Register 1 with MMX Register 2
MMX Register with Memory
PCMPEQB Packed Byte Compare for Equality
PCMPEQD Packed Dword Compare for Equality
PCMPEQW Packed Word Compare for Equality
PCMPGTB Pack Compare Greater Than Byte
MMX Register 2 to MMX Register 1
Memory to Register
MMX Register 2 to MMX Register 1
Memory to MMX Register
MMX Register 2 to MMX Register 1
Memory to MMX Register
MMX Register 2 to MMX Register 1
Memory to MMX Register
MMX Register 1 with MMX Register 2
MMX Register with Memory64
MMX Register 2 with MMX Register 1
Memory with MMX Register
MMX Register 2 with MMX Register 1
Memory with MMX Register
MMX Register 2 with MMX Register 1
Memory with MMX Register
MMX Register 2 to MMX Register 1
Memory with MMX Register
MMX™ Instructions
Table 8-28. MMX™ Instruction Set (Continued)
0FDD [11 mm1
mm2]
0FDD [mod mm r/m]
0FFD [11 mm1
mm2]
0FFD [mod mm r/m]
0FDB [11 mm1
mm2]
0FDB [mod mm r/m]
0FDF [11 mm1
mm2]
0FDF [mod mm r/m]
0FE0 [11 mm1
mm2]
0FE0 [mod mm r/m]
0FE3 [11 mm1
mm2]
0FE3 [mod mm r/m]
0F74 [11 mm1 mm2]
0F74 [mod mm r/m]
0F76 [11 mm1 mm2]
0F76 [mod mm r/m]
0F75 [11 mm1 mm2]
0F75 [mod mm r/m]
0F64 [11 mm1 mm2]
0F64 [mod mm r/m]
Opcode
MMX reg 1 [word] <--- sat --- (MMX reg 1 [word] + MMX reg 2
[word])
MMX reg [word] <--- sat --- (memory [word] + MMX reg [word])
MMX reg 1 [word] <--- MMX reg 1 [word] + MMX reg 2 [word]
MMX reg [word] <--- memory [word] + MMX reg [word]
MMX reg 1 [qword] --- MMX reg 1 [qword], <--- logic AND ---
MMX reg 2 [qword]
MMX reg [qword] memory [qword], <--- logic AND --- MMX reg
[qword]
MMX reg 1 [qword] NOT (MMX reg 1 [qword], <--- logic AND
--- MMX reg 2) [qword]
MMX reg [qword] --- NOT (MMX reg [qword], <--- logic AND
--- Memory [qword])
MMX reg 1 [byte] <--- round up --- (MMX reg 1 [byte] + MMX
reg 2 [byte] + 01h)/2
MMX reg 1 [byte] <--- round up --- (MMX reg 1 [byte] +
Memory64 [byte] + 01h)/2
MMX reg 1 [word] <--- round up --- (MMX reg 1[word] + MMX
reg 2 [word] + 01h)/2
MMX reg 1[word] <--- round up --- (MMX reg, [word] +
Memory64 [word] + 01h)/2
MMX reg 1 [byte] <--- FFh --- if MMX reg 1 [byte] = MMX reg 2
[byte]
MMX reg 1 [byte]<--- 00h --- if MMX reg 1 [byte] NOT = MMX
reg 2 [byte]
MMX reg [byte] <--- FFh --- if memory[byte] = MMX reg [byte]
MMX reg [byte] <--- 00h --- if memory[byte] NOT = MMX reg
[byte]
MMX reg 1 [dword] <--- FFFF FFFFh --- if MMX reg 1 [dword]
= MMX reg 2 [dword]
MMX reg 1 [dword]<--- 0000 0000h ---if MMX reg 1[dword]
NOT = MMX reg 2 [dword]
MMX reg [dword] <--- FFFF FFFFh --- if memory[dword] =
MMX reg [dword]
MMX reg [dword] <--- 0000 0000h --- if memory[dword] NOT
= MMX reg [dword]
MMX reg 1 [word] <--- FFFFh --- if MMX reg 1 [word] = MMX
reg 2 [word]
MMX reg 1 [word]<--- 0000h --- if MMX reg 1 [word] NOT =
MMX reg 2 [word]
MMX reg [word] <--- FFFFh --- if memory[word] = MMX reg
[word]
MMX reg [word] <--- 0000h --- if memory[word] NOT = MMX
reg [word]
MMX reg 1 [byte] <--- FFh --- if MMX reg 1 [byte] > MMX reg 2
[byte]
MMX reg 1 [byte]<--- 00h --- if MMX reg 1 [byte] NOT > MMX
reg 2 [byte]
MMX reg [byte] <--- FFh --- if memory[byte] > MMX reg [byte]
MMX reg [byte] <--- 00h --- if memory[byte] NOT > MMX reg
[byte]
Operation
33234H
Clock Ct
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Notes
661