ALXD800EEXJCVD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJCVD C3 Datasheet - Page 339

• Manufacturer Part Number: ALXD800EEXJCVD C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJCVD C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Display Controller Register Descriptions
6.6.9
6.6.9.1
DC Memory Offset 084h
Type
Reset Value
This register is used to set a base address for the graphics memory region. The value in this register is added to all outgo-
ing memory addresses. Because the base address must be aligned to a 16 MB region, only bits [31:24] of this register are
used.
6.6.9.2
DC Memory Offset 088h
Type
Reset Value
AMD Geode™ LX Processors Data Book
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31:20
19:11
31:12
10:0
Bit
Bit
DC GLIU0 Memory Offset (DC_GLIU0_MEM_OFFSET)
GLIU Control Registers
DC Dirty/Valid RAM Control (DC_DV_CTL)
Name
GLIU0_
MEM_OFFSET
RSVD
DV_RAM_AD
Name
DV Address
Offset
GLIU0_MEM_OFFSET
R/W
00000000h
R/W
00000000h
DV Address Offset
Description
GLIU0 Memory Offset. Base address (1 MB aligned) for the graphics memory region.
This value is added to all outgoing memory addresses.
Reserved. Equal to 0.
DV RAM Address. This value is used to allow direct software access to the Dirty/Valid
(DV) RAM. The address must be written in this location before reading or writing the DV
RAM Access Register (DC Memory Offset 08Ch).
Description
DV Address Offset. When the DV RAM observes memory transactions, the
addresses correspond to memory controller device address space. However, the DV
RAM is organized based on the internal DC device address space. To account for this,
the value indicated by this field is shifted to correspond to address bits [31:12], and
then subtracted from memory addresses before determining an offset into the DV
RAM. When programming the value in this field, software must calculate the sum of the
GLIU0_MEM_OFFSET (DC Memory Offset 084h[31:24] and the appropriate Physical-
to-Device descriptor(s) in GLIU0.
DC_GLIU0_MEM_OFFSET Bit Descriptions
DC_GLIU0_MEM_OFFSET Register Map
DC_DV_CTL Register Map
DV_CTL Bit Descriptions
RSVD
9
9
8
8
33234H
7
7
DV_RAM_AD
6
6
RSVD
5
5
4
4
3
3
2
2
1
1
339
0
0