ALXD800EEXJCVD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJCVD C3 Datasheet - Page 371

• Manufacturer Part Number: ALXD800EEXJCVD C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJCVD C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Display Controller Register Descriptions
Table 6-55 illustrates the various frame buffer addressing schemes. In the table, MAx represents the frame buffer memory
address signals, Ax represents the CRTC address counter signals, RSx represents row scan counter output bits. The
binary value in the column headings is a concatenation of the DWORD Mode and Byte Mode bits. (i.e., {DWORD Mode,
ByteMode} in verilog.)
AMD Geode™ LX Processors Data Book
Frame Buffer Memory Address Bit
Bit
1
0
Name
SL_RSCBT
SL_A13
MA10
MA11
MA12
MA13
MA14
MA15
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
CRTC Mode Control Register Bit Descriptions (Continued)
Description
Select Row Scan Bit. This bit determines which CRTC signal appears on the MA14
address bit sent to the frame buffer memory. If this bit is a 0, bit 1 of the Row Scan
counter appears on MA14. If this bit is a 1, then CRTC address counter bit 14, 13, or 12
appears on MA14. See Table 6-55 on page 371 for more information.
Select A13. This bit determines which CRTC signal appears on the MA13 address bit
sent to the frame buffer memory. If this bit is a 0, bit 0 of the Row Scan counter appears
on MA13. If this bit is a 1, then CRTC address counter bit 13, 12, or 11 appears on MA13.
See Table 6-55 on page 371 for more information.
Table 6-55. CRTC Memory Addressing Modes
Byte Mode (01)
A13 or RS0
A14 or RS1
A10
A11
A12
A15
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Word Mode (00)
A12 or RS0
A13 or RS1
A15 or A13
A10
A11
A14
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
33234H
DWORD Mode (1X)
A11 or RS0
A12 or RS1
A12
A13
A10
A13
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
371