ALXD800EEXJCVD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJCVD C3 Datasheet - Page 385
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ALXD800EEXJCVD C3
Manufacturer Part Number
ALXD800EEXJCVD C3
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.ALXD800EEXJCVD_C3.pdf
(680 pages)
Specifications of ALXD800EEXJCVD C3
Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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Display Controller Register Descriptions
6.6.23.1 ExtendedRegisterLock
CRTC Index
Type
Reset Value
6.6.23.2 ExtendedModeControl
CRTC Index
Type
Reset Value
6.6.23.3 ExtendedStartAddress
CRTC Index
Type
Reset Value
AMD Geode™ LX Processors Data Book
Bit
7:0
Bit
7:3
2:1
Bit
7:6
5:0
0
Name
LOCK
Name
RSVD
VG_RG_MAP
PACK_CH4
Name
RSVD
ST_AD_RG
[21:16]
030h
R/W
043h
R/W
00h
044h
R/W
00h
FFh
ExtendedRegisterLock Register Bit Descriptions
Description
Lock. A value of 4Ch unlocks the extended registers. Any other value locks the extended
registers so they are read only. If the extended registers are currently locked, a read to
this register will return FFh. If they are unlocked, a read will return 0.
Description
Reserved.
DC Register Mapping. These bits determine the DC register visibility within the standard
VGA memory space (A0000h-BFFFFh). Note that the VGA address space control bits
override this feature. If the Miscellaneous Output register RAM Enable bit is 0, all VGA
memory space is disabled. Or, if the Memory Map bits of the Graphics Miscellaneous
register are set the same as these bits, then the VGA frame buffer memory will appear in
this space instead of the GUI registers.
00: Disabled
01: A0000h
10: B0000h
11: B8000h
Packed Chain4: When this bit is set, the chain4 memory mapping will not skip DWORDs
as in true VGA. Host reads and writes to frame buffer DWORDs are contiguous. When
this bit is 0, host accesses behave normally and access 1 DWORD out of every 4. Note
that this bit has no effect on the VGA display refresh activity. This bit is only intended to
provide a front end for packed SVGA modes being displayed by DC.
ExtendedStartAddress Register Bit Descriptions
Description
Reserved.
Start Address Register Bits [21:16]. Start Address Register Bits [23:18]: These bits
extend the VGA start address to 24 bits. Bits [17:10] are in Start Address Hi (Index 0Ch),
and bits [9:2] are in Start Address Lo (Index 0Ch).
ExtendedModeControl Register Bit Descriptions
33234H
385
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