ALXD800EEXJCVD C3 AMD (ADVANCED MICRO DEVICES), ALXD800EEXJCVD C3 Datasheet - Page 462

• Manufacturer Part Number: ALXD800EEXJCVD C3
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ALXD800EEXJCVD C3

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.9
6.9.1
• VESA 1.1, 2.0 and BT.601, BT.656 compliant, 150 MHz
• 8/16-bit BT.601 type input video with HSYNC and
• 8-bit message and streaming video transfer mode
• Video data stored in linear or planar buffers
• Even line or even field decimation (4:2:2 -> 4:2:0 transla-
• Automatic paging for multi-frame storage
462
Input
YUV 4:2:2 Interlaced (8/16-bit)
SD/HD
YUV 4:2:2 Progressive
(8/16-bit)
SD/HD
YUV 4:2:0
VBI Data (8/16-bit)
Ancillary Data (8/16-bit)
Message Data (8-bit only)
Streaming Data (8-bit only)
(excludes host interface).
— Standard 9 or 17 pin interface (8/16 data + clock)
— 8/16-bit BT.656 video
— TASK A/B video and VBI (two video streams)
— 8/16-bit ancillary data
— HD capable (up to 1280x720 progressive scan,
— VIP 1.1 compatible mode (8 bit)
VSYNC
— (8 + clock + control on vid[10:8])
tion)
1920x1080 interlaced)
Video Input Port
Features
33234H
(to memory)
YUV 4:2:2
YUV 4:2:2
YUV 4:2:2
YUV 4:2:2
YUV 4:2:0
YUV 4:2:0
YUV 4:2:2
YUV 4:2:2
YUV 4:2:0
YUV 4:2:0
MSG Data
RAW Data
ANC Data
VBI Data
Output
Table 6-72.
Linear, Single Frame Buffer
Planar, Single Frame Buffer
Linear, Odd/Even Field Buffers
Planar, Odd/Even Field Buffers
Planar, Single Frame Buffer
Planar, Odd/Even Field Buffers
Linear, Single Frame Buffer
Planar, Single Frame Buffer
Planar, Single Frame Buffer
Linear
Linear
Linear, Circular Buffer
Linear, Dual Buffers
Linear, Dual Buffers
Memory Storage
VIP Capabilities
• Provides full frame buffer generation from interlaced
• Mutli-burst GLIU packets (programmable)
• Internal loopback using VOP outputs as source data
• vip_sync_to_pin output pin to request next frame or data
• vip_sync_to_vg output to DC/VP for frame synchroniza-
• frame_to_vg output to DC/VP for frame synchronization
• vip_int output for interrupt generation on frame/field/line
6.9.1.1
input (Weave)
packet from external data source (GenLock)
tion (VSYNC indication)
(odd/even field indication)
boundaries
— System goals:
— 150 MHz video interface
— 400 MHz GLIU interface
— Adequate GLIU bandwidth in HD capture mode (HD
— GLIU Latency requirements
VIP requires ~20 million QWORDs/sec)
Performance Metrics
AMD Geode™ LX Processors Data Book
Not Applicable
Bob
Standard Mode
Not Applicable
SC1200 Compatible
Message Data
Supports
Weave
Not Applicable
Rotation/Weave
Rotation/Bob
Rotation
VBI Data
Ancillary Data
RAW Data
Video Input Port
Task
A or B
A or B
A or B
A or B
A or B
A or B
A or B
A or B
A or B
A or B
A or B
N/A
N/A
N/A