EP4SGX290KF40C3N Altera, EP4SGX290KF40C3N Datasheet - Page 109
EP4SGX290KF40C3N
Manufacturer Part Number
EP4SGX290KF40C3N
Description
IC STRATIX IV GX 290K 1517FBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
Specifications of EP4SGX290KF40C3N
Number Of Logic Elements/cells
291200
Number Of Labs/clbs
11648
Total Ram Bits
17248
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1517-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2624
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Operational Mode Descriptions
Figure 4–19. Multiply Accumulate Mode Shown for a Half DSP Block
Note to
(1) Block output for saturation overflow of chainout.
February 2011 Altera Corporation
accum_sload
dataa_0[ ]
datab_0[ ]
dataa_1[ ]
datab_1[ ]
dataa_2[ ]
datab_2[ ]
dataa_3[ ]
datab_3[ ]
Figure
Multiply Accumulate Mode
4–19:
Half-DSP Block
clock[3..0]
In multiply accumulate mode, the second-stage adder is configured as a 44-bit
accumulator or subtractor. The output of the DSP block is looped back to the
second-stage adder and added or subtracted with the two outputs of the first-stage
adder block according to
configured to operate in multiply accumulate mode.
A single DSP block can implement up to two independent 44-bit accumulators.
ena[3..0]
aclr[3..0]
+
+
output_saturate
output_round
Equation 4–3 on page
signa
signb
+
4–5.
Figure 4–19
chainout_sat_overflow (1)
Stratix IV Device Handbook Volume 1
shows the DSP block
44
result[ ]
4–29
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