EP4SGX290KF40C3N Altera, EP4SGX290KF40C3N Datasheet - Page 940
EP4SGX290KF40C3N
Manufacturer Part Number
EP4SGX290KF40C3N
Description
IC STRATIX IV GX 290K 1517FBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
Specifications of EP4SGX290KF40C3N
Number Of Logic Elements/cells
291200
Number Of Labs/clbs
11648
Total Ram Bits
17248
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1517-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2624
Available stocks
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Part Number
Manufacturer
Quantity
Price
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5–94
Dynamic Reconfiguration Examples
Figure 5–41. Dynamic Reconfiguration Configuration for the S4GX230 Device (Example 1)
Stratix IV Device Handbook Volume 2: Transceivers
Example 1
The following examples help to describe the dynamic reconfiguration feature.
Consider a design with the following configuration:
■
■
■
Figure 5–41
Seven regular transceiver channels in Basic functional mode. You can configure
the seven regular transceiver channels from 2.5 Gbps to 5 Gbps and vice versa
using a single CMU.
Four channels in Basic (PMA Direct) functional mode. You can reconfigure the
four PMA-only channels from 3.125 Gbps to 5 Gbps and vice versa.
You can reconfigure the PMA controls for any one of these channels.
Regular Transceiver Channels
PMA-Only Channels
Transceiver Block GXBR0
Transceiver Block GXBR1
Transceiver Block GXBR2
shows the arrangement of these channels in the S4GX230 device.
ATX R0 PLL Block
CMU1 Channel
CMU0 Channel
CMU1 Channel
CMU0 Channel
CMU1 Channel
CMU0 Channel
Channel 2
Channel 0
Channel 2
Channel 0
Channel 3
Channel 1
Channel 2
Channel 0
Channel 3
Channel 1
Channel 3
Channel 1
Seven regular transceiver channels
use a single CMU0 PLL (GXBR2)
in the design
Four PMA-Only channels use a
single CMU0 PLL (GXBR0)
in the design
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Examples
February 2011 Altera Corporation
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