EP4SGX290KF40C3N Altera, EP4SGX290KF40C3N Datasheet - Page 727
EP4SGX290KF40C3N
Manufacturer Part Number
EP4SGX290KF40C3N
Description
IC STRATIX IV GX 290K 1517FBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
Specifications of EP4SGX290KF40C3N
Number Of Logic Elements/cells
291200
Number Of Labs/clbs
11648
Total Ram Bits
17248
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1517-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2624
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 2: Transceiver Clocking in Stratix IV Devices
FPGA Fabric-Transceiver Interface Clocking
Figure 2–30. FPGA Fabric-Transmitter Interface Clocking in a x4 Bonded Channel Configuration
Note to
(1) The green lines represent the parallel PCS clock.
February 2011 Altera Corporation
Figure
2–30:
and Control
and Control
and Control
and Control
Channel 2
Channel 3
Channel 1
Channel 0
TX Data
TX Data
TX Data
TX Data
Logic
Logic
Logic
Logic
Bonded Channel Configuration
In ×4 and ×8 bonded channel configurations, all channels within the transceiver block
are identical. The Quartus II software automatically drives the write port of the
transmitter phase compensation FIFO in all channels with the coreclkout signal. Use
the coreclkout signal to clock the transmitter data and control logic for all four
channels in the FPGA fabric.
Figure 2–30
channel configuration.
FPGA
Fabric
tx_coreclk[1]
tx_coreclk[0]
tx_coreclk[2]
tx_coreclk[3]
shows the FPGA fabric-Transmitter interface clocking in a ×4 bonded
coreclkout
Reference
Clock
Input
/2
CMU0 PLL
CMU1 PLL
wrclk
wrclk
Compensation
wrclk
wrclk
Compensation
Compensation
Compensation
TX Phase
TX Phase
TX Phase
TX Phase
FIFO
FIFO
FIFO
FIFO
rdclk
rdclk
rdclk
rdclk
Divider
CMU0
Clock
/2
/2
/2
/2
Stratix IV Device Handbook Volume 2: Transceivers
Parallel PCS Clock
Parallel PCS Clock
Transmitter Channel PCS
Parallel PCS Clock
Parallel PCS Clock
Transmitter Channel PCS
Transmitter Channel PCS
Transmitter Channel PCS
CMU1 Channel
CMU0 Channel
Channel 2
Channel 3
Channel 0
Channel 1
(Note 1)
2–55
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