EP4SGX290KF40C3N Altera, EP4SGX290KF40C3N Datasheet - Page 661
EP4SGX290KF40C3N
Manufacturer Part Number
EP4SGX290KF40C3N
Description
IC STRATIX IV GX 290K 1517FBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
Specifications of EP4SGX290KF40C3N
Number Of Logic Elements/cells
291200
Number Of Labs/clbs
11648
Total Ram Bits
17248
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1517-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2624
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Port Lists
Table 1–74. Stratix IV GX and GT ALTGX Megafunction Ports: Receiver Ports (Part 6 of 7)
February 2011 Altera Corporation
rx_coreclk
rx_phase_comp_fifo_
error
Receiver Physical Media Attachment (PMA)
rx_datain
rx_cruclk
rx_pll_locked
rx_freqlocked
rx_locktodata
Port Name
Output
Output
Output
Output
Input/
Input
Input
Input
Input
coreclkout for
Synchronous to
bonded modes.
tx_clkout for
tx_clkout or
Asynchronous
Asynchronous
Asynchronous
Clock Domain
coreclkout.
Clock signal
non-bonded
Clock signal
modes.
signal
signal
signal
N/A
Optional read clock port for the receiver phase
compensation FIFO.
■
■
Receiver phase compensation FIFO full or
empty indicator.
■
Receiver serial data input port.
Input reference clock for the receiver clock and
data recovery.
Receiver CDR lock-to-reference indicator.
■
■
Receiver CDR lock mode indicator.
■
■
Receiver CDR lock-to-data mode control signal.
■
■
If not selected—the Quartus II software
automatically selects
rx_clkout/tx_clkout/
coreclkout as the read clock for the
receiver phase compensation FIFO.
If selected—drive this port with a clock that
has 0 PPM difference with respect to
rx_clkout/tx_clkout/
coreclkout.
A high level—the receiver phase
compensation FIFO is either full or empty.
A high level—the receiver CDR is locked to
the input reference clock.
A low level—the receiver CDR is not locked
to the input reference clock.
A high level—the receiver CDR is in
lock-to-data mode.
A low level—the receiver CDR is in
lock-to-reference mode.
When asserted high—the receiver CDR is
forced to lock-to-data mode.
When de-asserted low—the receiver CDR
lock mode depends on the
rx_locktorefclk signal level.
Stratix IV Device Handbook Volume 2: Transceivers
Description
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Scope
1–217
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