EP4SGX290KF40C3N Altera, EP4SGX290KF40C3N Datasheet - Page 128

EP4SGX290KF40C3N

Manufacturer Part Number

EP4SGX290KF40C3N

Description

IC STRATIX IV GX 290K 1517FBGA

Manufacturer

Altera

Series

Stratix® IV GXr

Datasheets

1.EP4SGX110DF29C3N.pdf (80 pages)

2.EP4SGX110DF29C3N.pdf (1154 pages)

3.EP4SGX110DF29C3N.pdf (432 pages)

4.EP4SGX110DF29C3N.pdf (22 pages)

5.EP4SGX110DF29C3N.pdf (30 pages)

6.EP4SGX110DF29C3N.pdf (72 pages)

Specifications of EP4SGX290KF40C3N

Number Of Logic Elements/cells

291200

Number Of Labs/clbs

11648

Total Ram Bits

17248

Number Of I /o

744

Voltage - Supply

0.87 V ~ 0.93 V

Mounting Type

Surface Mount

Operating Temperature

0°C ~ 85°C

Package / Case

1517-FBGA

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Number Of Gates

Other names

544-2624

Available stocks

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Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

EP4SGX290KF40C3N

Manufacturer:

Altera

Quantity:

10 000

Company:

BOSTOCK HK LIMITED

Part Number:

EP4SGX290KF40C3N

Manufacturer:

ALTERA

Company:

BOSTOCK HK LIMITED

Part Number:

EP4SGX290KF40C3NB

Manufacturer:

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5–12

Table 5–3. Clock Input Pin Connectivity to the RCLK Networks (Part 2 of 2)

Table 5–4. Device PLLs and PLL Clock Pin Drivers

Stratix IV Device Handbook Volume 1

RCLK [34, 40]

RCLK [33, 37, 39, 43]

RCLK [32, 36, 38, 42]

RCLK [47, 51, 57, 61]

RCLK [46, 50, 56, 60]

RCLK [45, 49, 53, 55,

59, 63]

RCLK [44, 48, 52, 54,

58, 62]

CLK0

CLK1

CLK2

CLK3

CLK4

CLK5

CLK6

CLK7

CLK8

CLK9

CLK10

CLK11

CLK12

CLK13

CLK14

CLK15

Notes to

(1) For single-ended clock inputs, only the CLK<#>p pin has a dedicated connection to the PLL. If you use the CLK<#>n pin, a global clock is used.

(2) For the availability of the clock input pins in each device density, refer to the “Stratix IV Device Pin-Out Files” section of the

(3) These are non-compensated clock input paths. For the compensated input for these PLLs, use the corresponding PLL_[L, R][1,4]_CLK input

Dedicated Clock

CLK (p/n Pins)

Altera Devices

pin.

Input Pin

Clock Resource

Table

Clock Input Connections to the PLLs

5–4:

site.

Table 5–4

—

(3)

—

lists the dedicated clock input pin connectivity to Stratix IV PLLs.

—

(3)

(Note

—

1),

—

(2)

—

PLL Number

—

CLK (p/n Pins)

—

Chapter 5: Clock Networks and PLLs in Stratix IV Devices

—

(3)

—

Clock Networks in Stratix IV Devices

February 2011 Altera Corporation

—

(3)

Pin-Out Files for

—

EP4SGX290KF40C3N Altera, EP4SGX290KF40C3N Datasheet - Page 128

EP4SGX290KF40C3N

Specifications of EP4SGX290KF40C3N

Available stocks

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