EP4SGX290KF40C3N Altera, EP4SGX290KF40C3N Datasheet - Page 827
![IC STRATIX IV GX 290K 1517FBGA](/photos/6/73/67341/ds-1517fbga-1_3_sml.jpg)
EP4SGX290KF40C3N
Manufacturer Part Number
EP4SGX290KF40C3N
Description
IC STRATIX IV GX 290K 1517FBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
Specifications of EP4SGX290KF40C3N
Number Of Logic Elements/cells
291200
Number Of Labs/clbs
11648
Total Ram Bits
17248
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1517-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2624
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 4: Reset Control and Power Down in Stratix IV Devices
Transceiver Reset Sequences
February 2011 Altera Corporation
As shown in
manual lock mode:
1. After power up, assert pll_powerdown for a minimum period of t
2. Keep the tx_digitalreset, rx_analogreset, rx_digitalreset, and
3. After the transmitter PLL locks, as indicated by the pll_locked signal going high
4. Wait for at least t
5. De-assert rx_digitalreset at least t
time between markers 1 and 2).
rx_locktorefclk signals asserted and the rx_locktodata signal de-asserted
during this time period. After you de-assert the pll_powerdown signal, the
transmitter PLL starts locking to the transmitter input reference clock.
(marker 3), de-assert tx_digitalreset. For receiver operation, wait for the busy
signal to be de-asserted. At this point rx_analogreset is de-asserted. When
rx_analogreset is de-asserted, the receiver CDR starts locking to the receiver
input reference clock because rx_locktorefclk is asserted.
rx_pll_locked signal goes high, then de-assert the rx_locktorefclk signal. At the
same time, assert the rx_locktodata signal (marker 8). At this point, the receiver
CDR enters lock-to-data mode and the receiver CDR starts locking to the received
data.
after asserting the rx_locktodata signal.
Figure
4–11, perform the following reset procedure for the receiver in
LTR_LTD_Manual
(the time between markers 7 and 8) after the
LTD_Manual
Stratix IV Device Handbook Volume 2: Transceivers
(the time between markers 8 and 9)
pll_powerdown
(the
4–21
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