EP4SGX290KF40C3N Altera, EP4SGX290KF40C3N Datasheet - Page 735
![IC STRATIX IV GX 290K 1517FBGA](/photos/6/73/67341/ds-1517fbga-1_3_sml.jpg)
EP4SGX290KF40C3N
Manufacturer Part Number
EP4SGX290KF40C3N
Description
IC STRATIX IV GX 290K 1517FBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
Specifications of EP4SGX290KF40C3N
Number Of Logic Elements/cells
291200
Number Of Labs/clbs
11648
Total Ram Bits
17248
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1517-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2624
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
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Chapter 2: Transceiver Clocking in Stratix IV Devices
FPGA Fabric-Transceiver Interface Clocking
Figure 2–33. FPGA Fabric-Receiver Interface Clocking for Example 6
Note to
(1) The green lines represent the low-speed parallel clock and the blue lines represent the high-speed serial clock.
February 2011 Altera Corporation
Figure
and Status
and Status
and Status
Channel 3
and Status
Channel 1
Channel 0
Channel 2
RX Data
RX Data
RX Data
RX Data
Logic
Logic
Logic
Logic
2–33:
FPGA
Fabric
rx_coreclk[0]
rx_coreclk[2]
rx_coreclk[1]
rx_coreclk[3]
Figure 2–33
tx_clkout[2]
tx_clkout[0]
Reference
shows the FPGA fabric-Receiver interface clocking for Example 6.
Reference
Clock
Clock
Compensation
Compensation
Compensation
Compensation
rdclk
rdclk
CMU1
CMU0
rdclk
rdclk
RX Phase
RX Phase
PLL
PLL
RX Phase
RX Phase
FIFO
FIFO
FIFO
FIFO
wrclk
wrclk
wrclk
wrclk
/2
/2
/2
/2
(Note 1)
Low-Speed Parallel Clock
Low-Speed Parallel Clock
Low-Speed Parallel Clock
Low-Speed Parallel Clock
Receiver Channel PCS
Receiver Channel PCS
Receiver Channel PCS
Receiver Channel PCS
Stratix IV Device Handbook Volume 2: Transceivers
CMU1 Channel
CMU0 Channel
Channel 1
Channel 3
Channel 2
Channel 0
Transmitter Channel PMA
Transmitter Channel PMA
Transmitter Channel PMA
Receiver Channel PMA
Receiver Channel PMA
Transmitter Channel PMA
Receiver Channel PMA
Receiver Channel PMA
Divider Block
Divider Block
Local Clock
Divider Block
Local Clock
High-Speed Serial Clock
Divider Block
Local Clock
Local Clock
2–63
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