MC68EC000EI8 Freescale Semiconductor, MC68EC000EI8 Datasheet - Page 337

• Manufacturer Part Number: MC68EC000EI8
• Description: IC MPU 32BIT 85MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: M68000r

Specifications of MC68EC000EI8

• Processor Type: M680x0 32-Bit
• Speed: 8MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Core Size: 32 Bit
• Cpu Speed: 8MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

FDBcc
Instruction Format:
Instruction Fields:
MOTOROLA
15
1
0
Count Register field—Specifies data register that is used as the counter.
Conditional Predicate field—Specifies one of the 32 floating-point conditional tests as
Displacement field—Specifies the branch distance (from the address of the instruction
14
1
0
described in 3.6.2 Conditional Testing.
plus two) to the destination in bytes.
13
The terminating condition is like that defined by the UNTIL loop
constructs of high-level languages. For example: FDBOLT can
be stated as "decrement and branch until ordered less than".
There are two basic ways of entering a loop: at the beginning or
by branching to the trailing FDBcc instruction. If a loop structure
terminated with FDBcc is entered at the beginning, the control
counter must be one less than the number of loop executions
desired. This count is useful for indexed addressing modes and
dynamically specified bit operations. However, when entering a
loop by branching directly to the trailing FDBcc instruction, the
count should equal the loop execution count. In this case, if the
counter is zero when the loop is entered, the FDBcc instruction
does not branch, causing a complete bypass of the main loop.
When a BSUN exception occurs, a preinstruction exception is
taken by the main processor. If the exception handler returns
without modifying the image of the program counter on the stack
frame (to point to the instruction following the FDBcc), then it
must clear the cause of the exception (by clearing the NAN bit or
disabling the BSUN trap), or the exception will occur again im-
mediately upon return to the routine that caused the exception.
1
0
12
1
0
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
11
0
COPROCESSOR
Floating-Point Test Condition,
Decrement, and Branch
10
ID
0
(MC6888X, MC68040)
9
0
16-BIT DISPLACEMENT
8
0
0
NOTE
7
0
0
6
1
0
5
0
CONDITIONAL PREDICATE
4
0
Floating Point Instructions
3
1
2
FDBcc
REGISTER
COUNT
1
5-35
0