MC68EC000EI8 Freescale Semiconductor, MC68EC000EI8 Datasheet - Page 81

• Manufacturer Part Number: MC68EC000EI8
• Description: IC MPU 32BIT 85MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: M68000r

Specifications of MC68EC000EI8

• Processor Type: M680x0 32-Bit
• Speed: 8MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Core Size: 32 Bit
• Cpu Speed: 8MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Instruction Set Summary
3.1.5 Bit Manipulation Instructions
BTST, BSET, BCLR, and BCHG are bit manipulation instructions. All bit manipulation
operations can be performed on either registers or memory. The bit number is specified
either as immediate data or in the contents of a data register. Register operands are 32 bits
long, and memory operands are 8 bits long. Table 3-6 summarizes bit manipulation
operations; Z refers to the zero bit of the CCR.
3.1.6 Bit Field Instructions
The M68000 family architecture supports variable-length bit field operations on fields of up
to 32 bits. The BFINS instruction inserts a value into a bit field. BFEXTU and BFEXTS
extract a value from the field. BFFFO finds the first set bit in a bit field. Also included are
instructions analogous to the bit manipulation operations: BFTST, BFSET, BFCLR, and
BFCHG. Table 3-7 summarizes bit field operations.
NOTE: All bit field instructions set the CCR N and Z bits as shown for BFTST before performing the specified operation.
3-10
Instruction
Instruction
BFEXTU
BFEXTS
BFCHG
BFCLR
BFFFO
BFSET
BFTST
BCHG
BFINS
BCLR
BSET
BTST
<ea> {offset:width}, Dn
<ea> {offset:width}, Dn
<ea> {offset:width}, Dn
Dn,<ea> {offset:width}
Operand Syntax
Operand Syntax
<ea> {offset:width}
<ea> {offset:width}
<ea> {offset:width}
<ea> {offset:width}
#<data>,<ea>
#<data>,<ea>
#<data>,<ea>
#<data>,<ea>
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
Dn,<ea>
Dn,<ea>
Dn,<ea>
Dn,<ea>
Table 3-6. Bit Manipulation Operation Format
Table 3-7. Bit Field Operation Format
Operand Size
Operand Size
8, 32
8, 32
8, 32
8, 32
8, 32
8, 32
8, 32
8, 32
1–32
1–32
1–32
1–32
1–32
1–32
1–32
1–32
~ (<Bit Number> of Destination)
Bit of Destination
~ (<Bit Number> of Destination)
0
~ (<Bit Number> of Destination)
1
~ (<Bit Number> of Destination)
~ Field
0's
Field
Field
Scan for First Bit Set in Field; Offset
Dn
1's
Field MSB
Bit of Destination
Bit of Destination
Field
Field
Field
Dn; Sign-Extended
Dn; Zero-Extended
Field
N; ~ (OR of All Bits in Field)
Operation
Operation
Z
Z;
Z;
Z
MOTOROLA
Dn.
Z