MC68EC000EI8 Freescale Semiconductor, MC68EC000EI8 Datasheet - Page 98

• Manufacturer Part Number: MC68EC000EI8
• Description: IC MPU 32BIT 85MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: M68000r

Specifications of MC68EC000EI8

• Processor Type: M680x0 32-Bit
• Speed: 8MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Core Size: 32 Bit
• Cpu Speed: 8MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

intermediate value and still representable in the The following tie-case example shows how
the 67-bit mantissa allows the FPU to meet the error bound of the IEEE specification:
The LSB of the rounded result does not increment though the guard bit is set in the
intermediate result. The IEEE 754 standard specifies that tie cases should be handled in this
manner. If the destination data format is extended and there is a difference between the
infinitely precise intermediate result and the round-to-nearest result, the relative difference
is 2 – 64 (the value of the guard bit). This error is equal to half of the least significant bit’s
value and is the worst case error that can be introduced when using the RN mode. Thus, the
term one-half unit in the last place correctly identifies the error bound for this operation. This
error specification is the relative error present in the result; the absolute error bound is equal
to 2exponent x 2 – 64. The following example shows the error bound for the other rounding
modes:
The difference between the infinitely precise result and the rounded result is 2 – 64 + 2 – 65
+ 2 – 66, which is slightly less than 2 – 63 (the value of the LSB). Thus, the error bound for
this operation is not more than one unit in the last place. For all arithmetic operations, the
FPU meets these error bounds, providing accurate and repeatable results.
3.6 FLOATING-POINT POSTPROCESSING
Most operations end with a postprocessing step. The FPU provides two steps in
postprocessing. First, the condition code bits in the FPSR are set or cleared at the end of
each arithmetic operation or move operation to a single floating-point data register. The
condition code bits are consistently set based on the result of the operation. Second, the
FPU supports 32 conditional tests that allow floating-point conditional instructions to test
floating-point conditions in exactly the same way as the integer conditional instructions test
the integer condition code The combination of consistently set condition code bits and the
simple programming of conditional instructions gives the processor a very flexible, high-
performance method of altering program flow based on floating-point results. While reading
the summary for each instruction, it should be assumed that an instruction performs
postprocessing unless the summary specifically states that the instruction does not do so.
The following paragraphs describe postprocessing in detail.
MOTOROLA
Rounded-to-Nearest
Rounded-to-Nearest
Intermediate
Intermediate
Result
Result
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
Integer
Integer
x
x
x
x
63-Bit Fraction
63-Bit Fraction
xxx…x00
xxx…x00
xxx…x00
xxx…x00
Guard
Guard
1
0
1
0
Instruction Set Summary
Round
Round
0
0
1
0
Sticky
Sticky
0
0
1
0
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