MC68EC000EI8 Freescale Semiconductor, MC68EC000EI8 Datasheet - Page 93

• Manufacturer Part Number: MC68EC000EI8
• Description: IC MPU 32BIT 85MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: M68000r

Specifications of MC68EC000EI8

• Processor Type: M680x0 32-Bit
• Speed: 8MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Core Size: 32 Bit
• Cpu Speed: 8MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Instruction Set Summary
functions, software supports remainder and integer part; the FPU also supports the
nontranscendental operations of absolute value, negate, and test.
Most floating-point instruction descriptions include an operation table. This table lists the
resulting data types for the instruction based on the operand,s input. Table 3-20 is an
operation table example for the FADD instruction. The operation table lists the source
operand type along the top, and the destination operand type along the side. In-range
numbers are normalized, denormalized, unnormalized real numbers, or integers that are
converted to normalized or denormalized extended-precision numbers upon entering the
FPU.
For example, Table 3-20 illustrates that if both the source and destination operand are
positive zero, the result is also a positive zero. If the source operand is a positive zero and
the destination operand is an in-range number, then the ADD algorithm is executed to obtain
the result. If a label such as ADD appears in the table, it indicates that the FPU performs the
indicated operation and returns the correct result. Since the result of such an operation is
undefined, a NAN is returned as the result, and the OPERR bit is set in the FPSR EXC byte.
In addition to the data types covered in the operation tables for each floating-point
instruction, NANs can also be used as inputs to an arithmetic operation. The operation
tables do not contain a row and column for NANs because NANs are handled the same way
for all operations. If either operand, but not both operands, of an operation is a nonsignaling
NAN, then that NAN is returned as the result. If both operands are nonsignaling NANs, then
the destination operand nonsignaling NAN is returned as the result.
If either operand to an operation is a signaling NAN (SNAN), then the SNAN bit is set in the
FPSR EXC byte. If the SNAN exception enable bit is set in the FPCR ENABLE byte, then
the exception is taken and the destination is not modified. If the SNAN exception enable bit
is not set, setting the SNAN bit in the operand to a one converts the SNAN to a nonsignaling
NAN. The operation then continues as described in the preceding paragraph for
nonsignaling NANs.
3-22
NOTES:
1.If either operand is a NAN, refer to 1.6.5 NANs for more information.
2.Returns +0.0 in rounding modes RN, RZ, and RP; returns –0.0 in RM.
3.Sets the OPERR bit in the FPSR exception byte.
DESTINATION
In Range
Infinity
Zero
Table 3-20. Operation Table Example (FADD Instruction)
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
+
+
–
–
+
–
+
ADD
ADD
+inf
–inf
In Range
– + Zero –
ADD
+ 0.0
0.0
+inf
–inf
2
SOURCE
1
–0.0
0.0
2
+ Infinity –
+inf –inf
+inf –inf
+inf NAN
NAN
3
–inf
3
MOTOROLA