MC68EC000EI8 Freescale Semiconductor, MC68EC000EI8 Datasheet - Page 524

• Manufacturer Part Number: MC68EC000EI8
• Description: IC MPU 32BIT 85MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: M68000r

Specifications of MC68EC000EI8

• Processor Type: M680x0 32-Bit
• Speed: 8MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Core Size: 32 Bit
• Cpu Speed: 8MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Supervisor (Privileged) Instructions
PTEST
Operation:
Assembler
Syntax:
Attributes:
Description: This instruction searches the translation tables for the page descriptor
Condition Codes:
MMU Status Register:
6-70
Not affected.
corresponding to the test address in An and sets the bits of the MMU status register
according to the status of the descriptors. The upper address bits of the translated
physical address are also stored in the MMU status register. The PTESTR instruction
simulates a read access and sets the U-bit in each descriptor during table searches;
PTESTW simulates a write access and also sets the M-bit in the descriptors, the
address translation cache entry, and the MMU status register.
A matching entry in the address translation cache (data or instruction) specified by the
function code will be flushed by PTEST. Completion of PTEST results in the creation
of a new address translation cache entry. The specification of the function code for the
test address is in the destination function code (DFC) register. A PTEST instruction
with a DFC value of 0, 3, 4, or 7 is undefined and will return an unknown value in the
MMUSR.
Execution of the instruction continues until one of the following conditions occurs:
PHYSICAL ADDRESS
•
•
•
•
Match with one of the two transparent translation registers.
Transfer Error Assertion (physical transfer error)
Invalid Descriptor
Valid Page Descriptor
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
If Supervisor State
Else TRAP
PTESTR (An)
PTESTW (An)
Unsized
Then Logical Address Status
B
Test a Logical Address
(MC68040, MC68LC040)
G
U1
U0
S
MMUSR; Entry
CM
M
0
ATC
W
PTEST
MOTOROLA
T
R