MC68EC000EI8 Freescale Semiconductor, MC68EC000EI8 Datasheet - Page 501

• Manufacturer Part Number: MC68EC000EI8
• Description: IC MPU 32BIT 85MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: M68000r

Specifications of MC68EC000EI8

• Processor Type: M680x0 32-Bit
• Speed: 8MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Core Size: 32 Bit
• Cpu Speed: 8MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

PMOVE
Operation:
Assembler
Syntax:
Attributes:
Description: Moves the contents of the source effective address to the specified memory
MOTOROLA
management unit register or moves the contents of the memory management unit
register to the destination effective address.
The instruction is a quad-word (8 byte) operation for the CPU root pointer and the
supervisor root pointer. It is a long-word operation for the translation control register
and the transparent translation registers (TT0 and TT1). It is a word operation for the
MMU status register.
The PMOVEFD form of this instruction sets the FD-bit to disable flushing the address
translation cache when a new value loads into the supervisor root pointer, CPU root
pointer, TT0, TT1 or translation control register (but not the MMU status register).
Writing to the following registers has the indicated side effects:
CPU Root Pointer—When the FD-bit is zero, it flushes the address translation cache.
If the operand value is invalid for a root pointer descriptor, the instruction takes an
memory management unit configuration error exception after moving the operand to
the CPU root pointer.
Supervisor Root Pointer—When the FD-bit is zero, it flushes the address translation
cache. If the operand value is invalid as a root pointer descriptor, the instruction takes
an memory management unit configuration error exception after moving the operand
to the supervisor root pointer.
Translation Control Register—When the FD-bit is zero, it flushes the address transla-
tion cache. If the E-bit = 1, consistency checks are performed on the PS and TIx fields.
If the checks fail, the instruction takes an memory management unit configuration
exception after moving the operand to the translation control register. If the checks
pass, the translation control register is loaded with the operand and the E-bit is cleared.
TT0, TT1—When the FD-bit is zero, it flushes the address translation cache. It enables
or disables the transparent translation register according to the E-bit written. If the E-
bit = 1, the transparent translation register is enabled. If the E- bit = 0, the register is
disabled.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
If Supervisor State
PMOVE MRn, < ea >
PMOVE < ea > ,MRn
PMOVEFD < ea > ,MRn
Size = (Word, Long, Quad)
Then (Source)
Move to/from MMU Registers
(MC68030 only)
MRn or MRn
(Destination)
Supervisor (Privileged) Instructions
PMOVE
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