MC68EC000EI8 Freescale Semiconductor, MC68EC000EI8 Datasheet - Page 416

• Manufacturer Part Number: MC68EC000EI8
• Description: IC MPU 32BIT 85MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: M68000r

Specifications of MC68EC000EI8

• Processor Type: M680x0 32-Bit
• Speed: 8MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Core Size: 32 Bit
• Cpu Speed: 8MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Floating Point Instructions
FSGLDIV
5-114
Effective Address field—Determines the addressing mode for external operands.
R/M field—Specifies the source operand address mode.
Source Specifier field—Specifies the source register or data format.
Destination Register field—Specifies the destination floating- point data register.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in
0 — The operation is register to register.
1 — The operation is < ea > to register.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
the following table:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
*Only if < fmt > is byte, word, long, or single.
Addressing Mode
([bd,An,Xn],od)
([bd,An],Xn,od)
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
(bd,An,Xn)
(d
(d
8
(An) +
– (An)
,An,Xn)
(An)
16
Dn*
An
,An)
Single-Precision Divide
(MC6888X, MC68040)
Mode
000
010
011
100
101
110
110
110
110
—
reg. number:Dn
reg. number:An
reg. number:An
reg. number:An
reg. number:An
reg. number:An
reg. number:An
reg. number:An
reg. number:An
Register
—
Addressing Mode
([bd,PC,Xn],od)
([bd,PC],Xn,od)
(bd,PC,Xn)
(d
# < data >
(d
(xxx).W
(xxx).L
8
,PC,Xn)
16
,PC)
FSGLDIV
Mode
111
111
111
111
111
111
111
111
MOTOROLA
Register
000
001
100
010
011
011
011
011