MC68EC000EI8 Freescale Semiconductor, MC68EC000EI8 Datasheet - Page 551

• Manufacturer Part Number: MC68EC000EI8
• Description: IC MPU 32BIT 85MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: M68000r

Specifications of MC68EC000EI8

• Processor Type: M680x0 32-Bit
• Speed: 8MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Core Size: 32 Bit
• Cpu Speed: 8MHz
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

TBLU
TBLUN
Operation:
Assembler
Syntax:
Attributes:
Description: The TBLU and TBLUN instructions allow the efficient use of piecewise linear,
MOTOROLA
compressed data tables to model complex functions. The TBLU instruction has two
modes of operation: table lookup and interpolate mode and data register interpolate
mode.
For table lookup and interpolate mode, data register Dx 15 – 0 contains the
independent variable X. The effective address points to the start of a unsigned byte,
word, or long-word table containing a linearized representation of the dependent
variable, Y, as a function of X. In general, the independent variable, located in the low-
order word of Dx, consists of an 8-bit integer part and an 8-bit fractional part. An
assumed radix point is located between bits 7 and 8. The integer part, Dx 15 – 8, is
scaled by the operand size and is used as an offset into the table. The selected entry
in the table is subtracted from the next consecutive entry. A fractional portion of this
difference is taken by multiplying by the interpolation fraction, Dx 7 – 0. The adjusted
difference is then added to the selected table entry. The result is returned in the
destination data register, Dx.
Table Lookup and Interpolation (Unsigned)
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
Rounded:
Unrounded:
Where ENTRY(n) and ENTRY(n + 1) are either:
TBLU. < size > < ea > ,Dx
TBLUN. < size > < ea > ,Dx
TBLU. < size > Dym:Dyn, Dx
TBLUN. < size > Dym:Dyn, Dx
Size = (Byte, Word, Long)
ENTRY(n) + {(ENTRY(n + 1) – ENTRY(n)) x Dx 7 – 0} 256
ENTRY(n) x 256 + {(ENTRY(n + 1) – ENTRY(n)) x Dx 7 – 0}
1. Consecutive entries in the table pointed to by the < ea > and
2. The registers Dym, Dyn respectively
indexed by Dx 15 – 8
(CPU32)
SIZE or;
Result rounded
Result not rounded
Result rounded
Result not rounded
CPU32 Instructions
TBLUN
TBLU
7-11
Dx
Dx